Abstract: Picture display device including a field number conversion circuit provided with a synchronizing signal conversion circuit (4) in which the number of half-lines in a field of a television signal to be converted is counted by means of a counter (57). This number is passed on to a further counter (41) which counts at a rate which is different from that of the first-mentioned counter. The ratio between the counting rates of the counters is assumed to be equal to the ratio between the field numbers of a converted television signal and the television signal to be converted. Also in the case of possible deviations of the television signal to be converted from a standard signal, the further counter (41) places vertical synchronizing signals (V2) at the correct locations in the converted television signal.

Abstract: A circuit includes shift registers (SR1, SR2, SR3) having different write and read rates under the control of clock pulses of different frequencies so that they form part of a signal compression or signal expansion circuit for encoding from simultaneous signals to the time division multiplex signal and for decoding from the time division multiplex signal to the simultaneous signals, respectively. The circuit is an integrated circuit (IC) having shift registers (SR1, SR2, SR3) suitable for both series-in, parallel-out and parallel-in, series-out operation. The shift register (SR1) with the greatest number of register stages is coupled to parallel connections of at least two further shift registers (SR2, SR3) via a through-connection circuit SC1 for a parallel bi-directional connection of the register stages. The series inputs and series outputs of at least the three shift registers are each coupled to a connection terminal of the integrated circuit (IC).

Abstract: A picture pick-up or display device, respectively for recording a scene or displaying a scene image, respectively with the aid of a line raster formed by a plurality of horizontal lines which are consecutively scanned in opposite directions. The device comprises a line deflection circuit in which the line deflection coil forms part of a resonant circuit whose tuning frequency is substantially equal to half the line frequency, as a result of which the power dissipation is kept low. By means of a control circuit it is ensured that corresponding points of scanned lines are accurately in line in the vertical direction, the control circuit being arranged for causing a zero-crossing of the line deflection current and a signal which is characteristic of half the video information of a line substantially to coincide. The control circuit comprises an analogue delay element for setting the time position of this signal.