Abstract: The invention relates to production of alignment marks on a semiconductor wafer with the use of a light-opaque layer (17), wherein, before the light-opaque layer (17) is applied, by means of the etching of cavities, free-standing pillar groups are produced in the cavities and then the light-opaque layer (17) is applied. The pillars are produced with a height of above 1 ?m, which, moreover, is greater than a thickness of the light-opaque layer (17) to be applied in the cavities as layer portions (17x; 17y). The cavities are formed with a width such that they are filled only partly with the layer portions (17x; 17y) when the light-opaque layer (17) is applied. The high, freely positioned alignment marks produced by the method as pillar series (16x; 16y), having a plurality of individual pillars (16a; 16a?) in a cavity (12a, 12y), of a scribing trench on the semiconductor wafer are likewise described.

Abstract: A semiconductor component with straight insulation trenches formed in a semiconductor material providing semiconductor areas laterally insulated from each other. Each insulation trench has a uniform width along its longitudinal direction represented by a central line. The semiconductor component has an intersecting area into which at least three of the straight insulation trenches lead. A center of the intersecting area is defined as a point of intersection of the continuations of the center lines. A central semiconductor area disposed in the intersecting area is connected with one of the semiconductor areas and contains the center of the intersecting area.

Abstract: A semiconductor component with straight insulation trenches formed in a semiconductor material providing semiconductor areas laterally insulated from each other. Each insulation trench has a uniform width along its longitudinal direction represented by a central line. The semiconductor component has an intersecting area into which at least three of the straight insulation trenches lead. A center of the intersecting area is defined as a point of intersection of the continuations of the center lines. A central semiconductor area disposed in the intersecting area is connected with one of the semiconductor areas and contains the center of the intersecting area.

Abstract: The invention relates to production of alignment marks on a semiconductor wafer with the use of a light-opaque layer (17), wherein, before the light-opaque layer (17) is applied, by means of the etching of cavities, free-standing pillar groups are produced in the cavities and then the light-opaque layer (17) is applied. The pillars are produced with a height of above 1 ?m, which, moreover, is greater than a thickness of the light-opaque layer (17) to be applied in the cavities as layer portions (17x; 17y). The cavities are formed with a width such that they are filled only partly with the layer portions (17x; 17y) when the light-opaque layer (17) is applied. The high, freely positioned alignment marks produced by the method as pillar series (16x; 16y), having a plurality of individual pillars (16a; 16a?) in a cavity (12a, 12y), of a scribing trench on the semiconductor wafer are likewise described.

Abstract: The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically chip regions having different potentials from each other with the aid of isolation trenches (10). In order to prevent voltage rises at sharp edges on the bottom of the isolation trenches, said edges are rounded in a simple process, part of the insulating layer (2) being isotropically etched.

Abstract: Trenches are formed in an SOI wafer to isolate low-voltage and high-voltage elements in the wafer. The isolation trenches are formed with trench coverings that do not protrude above the trenches. Vertical in-trench and horizontal out-of-trench isolation layers are formed and the trenches are then filled to above the planar surface formed by the isolating layers. The filling is planarized and a portion of the filling located in the trench interior is removed. A portion of the isolation layers are then removed and a portion of the filling is removed so that the filler and the isolation layers in the trenches are at about the same level. A covering layer is then deposited. The covering layer extends above the surface of the wafer and into the trenches down to the filler and the isolation layers. The covering layer is additionally planarized to about the top of the trenches.

Abstract: An efficient method for the thermal oxidation of preferably silicon semiconductor wafers using LOCOS (local oxidation of silicon) processes is described. The mechanical stresses of the wafers are to be reduced. To this end, an oxidation method is proposed that comprises providing a substrate (1) having a front side (12) to be patterned and a rear side (13). The substrate is oxidized in two steps. In a first step the rear side (13) is covered by a layer (4) that inhibits or hampers the oxidation. During a second step of the oxidation the oxidation-hampering layer (4) is no longer present. During both steps an oxide thickness is obtained on the front side (12) that is greater than an oxide thickness obtained on the rear side (13).

Abstract: The invention relates to an isolation trench structure and a corresponding layout wherein the insulating properties of isolation trenches (10, 10?) in critical areas (at intersections and junctions) are improved. Flattened and/or rounded off corner areas (10a, 10b) of the semiconductor regions to be insulated are produced, the etching and filling behavior being adjusted to be similar to that in the areas outside the critical areas, a center island (18, 18?) being provided for adapting the effective trench width in the critical areas of transition. The isolation trench structure is suitable for semiconductor arrangements (smart power applications) in which large voltage differences occur between the regions (12, 12?) to be electrically insulated from each other and the corresponding components. Power components can be integrated on the same chip together with small-signal elements.

Abstract: The aim of the invention is to configure a photodetector (10) such that no disadvantages are created for processing low luminous intensities on detectors known in prior art, especially when monolithically integrating the evaluation electronics. Said aim is achieved by a photodetector for processing low luminous intensities, comprising a monolithically integrated transimpedance amplifier and monolithically integrated evaluation electronics. An actual photocell component (20) is assigned to the chip face onto which the light preferably falls. Electronic circuit components (30) are arranged on the opposite chip face. Electrical connections (40) between the photocell and the electronic circuit are provided with an extension in the direction running perpendicular to the chip normal.

Abstract: Trenches are formed in an SOI wafer to isolate low-voltage and high-voltage elements in the wafer. The isolation trenches are formed with trench coverings that do not protrude above the trenches. Vertical in-trench and horizontal out-of-trench isolation layers are formed and the trenches are then filled to above the planar surface formed by the isolating layers. The filling is planarized and a portion of the filling located in the trench interior is removed. A portion of the isolation layers are then removed and a portion of the filling is removed so that the filler and the isolation layers in the trenches are at about the same level. A covering layer is then deposited. The covering layer extends above the surface of the wafer and into the trenches down to the filler and the isolation layers. The covering layer is additionally planarized to about the top of the trenches.

Abstract: The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically chip regions having different potentials from each other with the aid of isolation trenches (10). In order to prevent voltage rises at sharp edges on the bottom of the isolation trenches, said edges are rounded in a simple process, part of the insulating layer (2) being isotropically etched.

Abstract: An efficient method for the thermal oxidation of preferably silicon semiconductor wafers using LOCOS (local oxidation of silicon) processes is described. The mechanical stresses of the wafers are to be reduced. To this end, an oxidation method is proposed that comprises providing a substrate (1) having a front side (12) to be patterned and a rear side (13). The substrate is oxidized in two steps. In a first step the rear side (13) is covered by a layer (4) that inhibits or hampers the oxidation. During a second step of the oxidation the oxidation-hampering layer (4) is no longer present. During both steps an oxide thickness is obtained on the front side (12) that is greater than an oxide thickness obtained on the rear side (13).

Abstract: Disclosed is a layer arrangement (4b, 5b, 9b, 10, 9a, 5a, 4a) within an insulating trench, which insulates circuits with little distortion while being suitable for electrically insulating high-voltage power components (7) relative to low-voltage logic elements (6) that are integrated on the same chip (1, 2, 3). Also disclosed is the production of a sequence of alternating vertical layers in a trench (T). The electric strength for high voltages is improved while the influence of defects created by distortions of substrate disks is prevented.

Abstract: The aim of the invention is to configure a photodetector (10) such that no disadvantages are created for processing low luminous intensities on detectors known in prior art, especially when monolithically integrating the evalation electronics. Said aim is achieved by a photodetector for processing low luminous intensities, comprising a monolithically integrated transimpedance amplifier and monolithically integrated evaluation electronics. An actual photocell component (20) is assigned to the chip face onto which the light preferably falls. Electronic circuit components (30) are arranged on the opposite chip face. Electrical connections (40) between the photocell and the electronic circuit are provided with an extension in the direction running perpendicular to the chip normal.

Abstract: Disclosed is a layer arrangement (4b, 5b, 9b, 10, 9a, 5a, 4a) within an insulating trench, which insulates circuits with little distortion while being suitable for electrically insulating high-voltage power components (7) relative to low-voltage logic elements (6) that are integrated on the same chip (1, 2, 3). Also disclosed is the production of a sequence of alternating vertical layers in a trench (T). The electric strength for high voltages is improved while the influence of defects created by distortions of substrate disks is prevented.

Abstract: An electrochemical actuator forms a sealed gas space inside of which there are a plurality of cells. Each cell has a solid electrode made from an electrochemically reversibly oxidizable material and a counter electrode. By applying a reversible direct current, an electrochemical reaction is initiated which results in a pressure increase or decrease in the gas space that can be used for generating movement. The manufacture of the actuator is simplified and manufacturing costs are lowered by providing a stackable spacer frame for each cell which is constructed of a material that is a relatively good heat conductor and an electric isolator. The rim of a metallic cell cup is attached to the spacer frame and a matrix soaked with an electrolyte is placed inside the cup. Each cell further has a solid electrode, a separator and a counter electrode which, together with the spacer frame, are assembled into a cell.