Abstract: The present invention relates to a method, to a computer program containing instructions and to an apparatus for performing a boot process for a system that supports redundant copies of boot images. In a first step, an active copy of the boot images is determined (S1). Then the active copy of the boot images is processed (S2). In response to a successful boot process, another copy of the boot images is then set (S3) as the active copy for a subsequent boot process.

Abstract: A flash memory device is re-partitioned over-the-air. A software component responsible for re-partitioning is received. The software component then generates a re-partitioning control structure in the flash memory device and executes re-partitioning steps. The executed re-partitioning steps and currently valid locations of data that needs to be moved in the flash memory device during re-partitioning are recorded in the re-partitioning control structure.

Abstract: A flash memory device is re-partitioned over-the-air. A software component responsible for re-partitioning is received. The software component then generates a re-partitioning control structure in the flash memory device and executes re-partitioning steps. The executed re-partitioning steps and currently valid locations of data that needs to be moved in the flash memory device during re-partitioning are recorded in the re-partitioning control structure.

Abstract: The present invention relates to a method, to a computer program containing instructions and to an apparatus for performing a boot process for a system that supports redundant copies of boot images. In a first step, an active copy of the boot images is determined (S1). Then the active copy of the boot images is processed (S2). In response to a successful boot process, another copy of the boot images is then set (S3) as the active copy for a subsequent boot process.

Abstract: Computer device(s), apparatus(es), and methods enable and/or perform interface independent test boot of a System on Chip (SoC). A test Direct Memory Access hardware unit (test DMA) and an Automatic Test Equipment (ATE) hardware unit suspend a processor core of the SoC, download a test case, perform a seamless switch into functional mode of the SoC, and execute the downloaded test case. The test DMA may mediate between the ATE and internal memory in the SoC.

Abstract: A processor includes logic to generate a wakeup code value for a deep sleep state in which the processor is powered down, store the wakeup code value to a first location in a power domain in which power is maintained in the deep sleep state, store the wakeup code value to a second location in a non-volatile memory device, and initiate entry into the deep sleep state. The processor also includes logic to begin execution of a wakeup sequence upon waking up from the deep sleep state. The wakeup sequence includes a determination of whether a value read from the second location and a value read from the first location match. If they do not match, the processor triggers an exception handling sequence, which may include a secure boot sequence. If they match, the processor continues executing the wakeup sequence without executing a secure boot sequence.

Abstract: Computer device(s), apparatus(es), and methods enable and/or perform interface independent test boot of a System on Chip (SoC). A test Direct Memory Access hardware unit (test DMA) and an Automatic Test Equipment (ATE) hardware unit suspend a processor core of the SoC, download a test case, perform a seamless switch into functional mode of the SoC, and execute the downloaded test case. The test DMA may mediate between the ATE and internal memory in the SoC.

Abstract: A radio communication device and a method for booting a radio communication device are provided. The radio communication device can be configured to load an operating system code of a processor during execution of an authentication procedure code. For example, a first portion of the operating system code can be loaded, then the authentication procedure code can be loaded after the loading of the first portion of the operating system code. After the initiation of an authentication procedure that is based on the authentication procedure code, then a second portion of the operating system code can be loaded.

Abstract: A processor includes logic to generate a wakeup code value for a deep sleep state in which the processor is powered down, store the wakeup code value to a first location in a power domain in which power is maintained in the deep sleep state, store the wakeup code value to a second location in a non-volatile memory device, and initiate entry into the deep sleep state. The processor also includes logic to begin execution of a wakeup sequence upon waking up from the deep sleep state. The wakeup sequence includes a determination of whether a value read from the second location and a value read from the first location match. If they do not match, the processor triggers an exception handling sequence, which may include a secure boot sequence. If they match, the processor continues executing the wakeup sequence without executing a secure boot sequence.

Abstract: In various embodiments of the invention, a radio communication device and a method for booting a radio communication device are provided. In an embodiment of the invention, an operating system code of a processor is loaded during execution of an authentication procedure code.

Abstract: A radio communication device and a method for booting a radio communication device are provided. The radio communication device can be configured to load an operating system code of a processor during execution of an authentication procedure code. For example, a first portion of the operating system code can be loaded, then the authentication procedure code can be loaded after the loading of the first portion of the operating system code. After the initiation of an authentication procedure that is based on the authentication procedure code, then a second portion of the operating system code can be loaded.

Abstract: For example, a circuit arrangement is provided comprising a clock generator configured to generate a clock signal, a circuit having a low power mode, and a controller, configured to receive, when the circuit is in the low power mode, a request specifying that the circuit should return from the low power mode and trigger the circuit to return from the low power mode when the number of clock cycles of the clock signal since the reception of the request has reached a threshold value.

Abstract: A magnetic random access memory is configured as a read/write memory and at least a first section of the magnetic random access memory is configured to be converted to a read only memory.

Abstract: For example, a circuit arrangement is provided comprising a clock generator configured to generate a clock signal, a circuit having a low power mode, and a controller, configured to receive, when the circuit is in the low power mode, a request specifying that the circuit should return from the low power mode and trigger the circuit to return from the low power mode when the number of clock cycles of the clock signal since the reception of the request has reached a threshold value.

Abstract: An apparatus and a method of controlling a processor clock frequency are provided. The apparatus comprises a hardware counter to count write accesses to a memory buffer during a predetermined period of time, a hardware comparator to compare a number of write accesses counted by the hardware counter with at least one predetermined threshold value, the hardware comparator further to generate a control signal, the control signal being dependent on a result of a comparison of a number of write accesses counted by the hardware counter with at least one predetermined threshold value performed by the hardware comparator, and a clock frequency setting circuit to set a clock frequency of a processor depending on the control signal.

Abstract: A magnetic random access memory is configured as a read/write memory and at least a first section of the magnetic random access memory is configured to be converted to a read only memory.

Abstract: A magnetic random access memory is configured as a read/write memory and at least a first section of the magnetic random access memory is configured to be converted to a read only memory.

Abstract: Embodiments relate generally to a radio communication device, to a receiver controller of a radio communication device, and to a method for searching for a radio cell. In an embodiment, a method for searching for a radio cell is provided. The method may include scanning at least one frequency band of a first radio access technology, scanning at least one frequency band of a second radio access technology, wherein the at least one frequency band of the second radio access technology at least partially overlaps with the at least one frequency band of the first radio access technology, wherein at least one frequency sub-band of the first radio access technology is not scanned in the at least one frequency band of the second radio access technology.

Abstract: A magnetic random access memory is configured as a read/write memory and at least a first section of the magnetic random access memory is configured to be converted to a read only memory.

Abstract: A communication device including a memory configured to store a plurality of device resource profiles, wherein each device resource profile specifies device resources of the communication device and is associated with a respective communication connection state of a plurality of communication connection states; a determining circuit configured to determine a communication connection state of a communication connection of the communication device; and a control circuit configured to set device resources of the communication device in accordance with the device resource profile associated with the communication connection state of the communication connection.