Abstract: A thyristor having a semiconductor body in which a p-doped emitter, an n-doped base, a p-doped base and an n-doped main emitter are arranged successively in a vertical direction starting from a rear face toward a front face. For buffering of the transient heating, a metallization is applied to the front face and/or to the rear face and includes at least one first section which has an area-specific heat capacity of more than 50 J·K?1·m?2 at each point.

Abstract: An integrated circuit and an arrangement including a semiconductor device and a connecting element and method for producing such an arrangement is disclosed. One embodiment provides a semiconductor element having a first contact face and a second contact face. The first contact face and the second contact face extend in a first lateral direction. An electrically conductive connecting element which has a third contact face electrically contacts the semiconductor element. The connecting element includes a trench system. A first trench of this trench system extends from the third contact face into the connecting element.

Abstract: Bipolar power semiconductor component comprising a p-type emitter and more highly doped zones in the p-type emitter, and production method The invention relates to a bipolar power semiconductor component comprising a semiconductor body (1), in which a p-doped emitter (8), an n-doped base (7), a p-doped base (6) and an n-doped main emitter (5) are arranged successively in a vertical direction (v). The p-doped emitter (8) has a number of heavily p-doped zones (82) having a locally increased p-type doping. The invention furthermore relates to a method for producing a power semiconductor component.

Abstract: A thyristor has a radiation-sensitive breakdown structure (20), a gate electrode (92) that is placed at a distance from the latter in a lateral direction and an ignition stage structure having at least one ignition stage (51, 91) equipped with an n-doped auxiliary emitter (51), which forms a pn-junction (55) together with the p-doped base (6), the thyristor being both electrically and radiation-ignited. In a method for contacting a thyristor that can be ignited by radiation with a gate electrode (92), a contact ram (200) that is adapted to the geometry of the gate electrode (92) is pressed against the thyristor. In a method for monitoring the ignition of a thyristor that is ignited by incident radiation, the electric voltage that is applied to the gate electrode (92) or the electrically conductive electrode (105, 201) is monitored.

Abstract: A main thyristor (1) has a recovery protection which is integrated into a drive thyristor (2) whose n-doped emitter (25) is electrically connected to a main thyristor control terminal (140). Moreover, the p-doped emitter (28) of the drive thyristor (2) is electrically connected to the p-doped emitter (18) of the main thyristor (1). Various optional measures for realizing a recovery protection are provided in this case. A method for producing a thyristor system having a main thyristor and a drive thyristor, the drive thyristor (2) having anode short circuits (211) involves introducing particles (230) into a target region (225) of the semiconductor body (200) of the drive thyristor (2), the distance between the target region (225) and a front side (201) of the semiconductor body (200) opposite to the rear side (202) being less than or equal to the distance between the p-doped emitter (28) and the front side (201).

Abstract: A thyristor has a semiconductor body (1), in which a p-doped emitter (8), an n-doped base (7), a p-doped base (6) and an n-doped main emitter (5) are arranged successively in a vertical direction, the p-doped base (6) having a resistance zone (65) with a predetermined electrical resistance (R.int) extending in a lateral direction (r) perpendicular to the vertical direction, an external resistor (30, R.ext) that is arranged or can be arranged outside the semiconductor body (1) being electrically connected in parallel with the resistance zone (65), and the external resistor (30) having, in a specific temperature range, a temperature coefficient whose magnitude is less than the magnitude of the temperature coefficient of the resistance zone (65) in the specific temperature range.

Abstract: A thyristor comprises a semiconductor body with a front and back face, an edge, a first semiconductor zone, embodied in the region of the rear face and a second semiconductor zone, adjacent to the first semiconductor zone, whereby the edge has a bevelled embodiment in the region of the transition between the first and second semiconductor zones, at least one third semiconductor zone, arranged in the region of the front face of the semiconductor body and at least one fourth semiconductor zone, arranged between the at least one third semiconductor zone and the second semiconductor zone. The fourth semiconductor zone terminates before the edge in the lateral direction of the semiconductor body, in order to reduce the amplification of a parasitic bipolar transistor formed in the region of the edge by the fourth semiconductor zone, the second semiconductor zone and the first semiconductor zone.

Abstract: A semiconductor component is arranged in a semiconductor body and has at least one integrated radially symmetrical lateral resistance having a location-dependent sheet resistance, the radial dependence of which is preferably configured such that the differential resistance dR is radially constant or the power dissipated in the resistance is radially constant.

Abstract: A semiconductor component is arranged in a semiconductor body and has at least one integrated radially symmetrical lateral resistance having a location-dependent sheet resistance, the radial dependence of which is preferably configured such that the differential resistance dR is radially constant or the power dissipated in the resistance is radially constant.

Abstract: The invention relates to a method for contacting SIPOS-passivated semiconductor zones on a semiconductor body, where the removal of the oxide layer from the wafer surface takes place at the same time as the oxide etching before SIPOS passivation. The double-layered SIPOS passivation consists here of a N-SIPOS layer and a O-SIPOS layer. For contact opening, only the N-SIPOS layer is removed by wet chemical etching. By annealing the previously vaporized and structured metallization, a good contact results which can also carry a high current. The process according to the invention involves a simple sequence of operations and an underetching of the passivation layers and the disadvantages resulting from this are reliably avoided.