Patents by Inventor Uwe Paul
Uwe Paul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973147Abstract: A power semiconductor component for voltage limiting includes a rear-side base zone electrically contacted with a rear-side electrode and a front-side base zone electrically contacted with a front-side electrode. At least one switch-on structure is embedded at least into one of the rear-side base zone and the front-side base zone and is electrically contacted by the electrode contacting the embedding base zone. At least one triggering structure is provided as a breakdown structure of a first type, present between the front-side and rear-side electrodes. At least one further triggering structure is provided as a breakdown structure of a second type, present between the front-side and rear-side electrodes. The front-side and rear-side electrodes are each electrically conductively pressure-contacted by an electrically conductive contact plate at least one of which functions as a heat sink for dissipating heat generated in the semiconductor body.Type: GrantFiled: February 8, 2022Date of Patent: April 30, 2024Assignee: Infineon Technologies Bipolar GmbH & Co. KGInventors: Juergen Schiele, Reiner Barthelmess, Uwe Kellner-Werdehausen, Sebastian Paul Sommer
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Publication number: 20200189982Abstract: A fireproof molding body having a hot side and a cold side opposite said hot side, wherein the fireproof molding body includes a first material with ceramic hollow sphere structures, wherein an amount of hollow sphere structures decreases from the hot side to the cold side. A method for producing a fireproof molding body in which a first material with ceramic hollow sphere structures is introduced into a casting mold and a grading of the hollow sphere structures is subsequently performed.Type: ApplicationFiled: November 7, 2017Publication date: June 18, 2020Applicant: Siemens AktiengesellschaftInventors: Tobias Buchal, Elke Henschel, Simon Kliesch, Christian Nikasch, Uwe Paul, Kang Qian, Alexander Schaufler, Martin Wilke
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Patent number: 10311186Abstract: Methodologies and a device for assessing integrated circuit and pattern for yield risk based on 3D simulation of semiconductor patterns are provided. Embodiments include generating, with a processor, a 3D simulation of semiconductor patterns; obtaining critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns; comparing the set of critical dimensions with predefined minimum dimensions; and yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step.Type: GrantFiled: April 12, 2016Date of Patent: June 4, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jaime Bravo, Vikrant Chauhan, Piyush Pathak, Shobhit Malik, Uwe Paul Schroeder
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Patent number: 10276674Abstract: One illustrative method disclosed includes, among other things, forming a sacrificial S/D contact structure above an S/D region of a transistor device, removing at least a portion of a gate cap and at least a portion of a gate sidewall spacer to define a gate contact cavity that is positioned entirely above the active region and exposes an upper surface of a gate structure of the transistor device, and forming an internal sidewall spacer within the gate contact cavity. The method also includes performing at least one process operation to remove at least the sacrificial S/D contact structure and define a S/D contact cavity, and forming a gate contact structure within the gate contact cavity that is conductively coupled to the gate structure and forming a S/D contact structure within the S/D contact cavity that is conductively coupled to the S/D region.Type: GrantFiled: June 28, 2016Date of Patent: April 30, 2019Assignee: GLOBALFOUNDRIES Inc.Inventor: Uwe Paul Schroeder
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Patent number: 10248754Abstract: An identification of a first area of an IC design surrounding a failure component is received; and, in response, a smaller portion of the first area is selected. The smaller portion also surrounds the failure component, is smaller than the first area, and contains less circuit components than the first area. The smaller portion is matched to other areas of the IC design to identify potentially undesirable patterns of the IC design that are the same size as the first area. Additionally, the potentially undesirable patterns are grouped into pattern categories, the pattern categories are matched to known good pattern categories, and the known good patterns are removed from the potentially undesirable patterns to leave potential failure patterns. The potential failure patterns of the IC design are then output.Type: GrantFiled: May 23, 2017Date of Patent: April 2, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Uwe Paul Schroeder, Fadi Batarseh, Karthik Krishnamoorthy, Ahmed Omran
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Publication number: 20180341739Abstract: An identification of a first area of an IC design surrounding a failure component is received; and, in response, a smaller portion of the first area is selected. The smaller portion also surrounds the failure component, is smaller than the first area, and contains less circuit components than the first area. The smaller portion is matched to other areas of the IC design to identify potentially undesirable patterns of the IC design that are the same size as the first area. Additionally, the potentially undesirable patterns are grouped into pattern categories, the pattern categories are matched to known good pattern categories, and the known good patterns are removed from the potentially undesirable patterns to leave potential failure patterns. The potential failure patterns of the IC design are then output.Type: ApplicationFiled: May 23, 2017Publication date: November 29, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: Uwe Paul Schroeder, Fadi Batarseh, Karthik Krishnamoorthy, Ahmed Omran
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Patent number: 10055535Abstract: Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database.Type: GrantFiled: September 27, 2016Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Piyush Pathak, Robert C. Pack, Wei-Long Wang, Karthik Krishnamoorthy, Fadi S. Batarseh, Uwe Paul Schroeder, Sriram Madhavan
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Publication number: 20180156046Abstract: A rotor blade for a gas turbine, the rotor blade having an aerofoil with a pressure side and an intake side which transition into a platform to which an attachment region is connected, the region having a fir tree spring which has a plurality of lateral toothed extensions arranged on the pressure side and the intake side, which extensions extend in an azimuthal direction. In addition, the azimuthal extent of one lateral toothed extension is reduced in an axial region of the lateral toothed extension, in which region the pressure load during operation exceeds a predefined threshold.Type: ApplicationFiled: April 27, 2016Publication date: June 7, 2018Applicant: Siemens AktiengesellschaftInventors: Fathi Ahmad, Nihal Kurt, Uwe Paul, Albrecht Rieger
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Publication number: 20180089357Abstract: Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database.Type: ApplicationFiled: September 27, 2016Publication date: March 29, 2018Applicant: GLOBALFOUNDRIES Inc.Inventors: Piyush PATHAK, Robert C. PACK, Wei-Long WANG, Karthik KRISHNAMOORTHY, Fadi S. BATARSEH, Uwe Paul SCHROEDER, Sriram MADHAVAN
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Publication number: 20170373161Abstract: One illustrative method disclosed includes, among other things, forming a sacrificial S/D contact structure above an S/D region of a transistor device, removing at least a portion of a gate cap and at least a portion of a gate sidewall spacer to define a gate contact cavity that is positioned entirely above the active region and exposes an upper surface of a gate structure of the transistor device, and forming an internal sidewall spacer within the gate contact cavity. The method also includes performing at least one process operation to remove at least the sacrificial S/D contact structure and define a S/D contact cavity, and forming a gate contact structure within the gate contact cavity that is conductively coupled to the gate structure and forming a S/D contact structure within the S/D contact cavity that is conductively coupled to the S/D region.Type: ApplicationFiled: June 28, 2016Publication date: December 28, 2017Inventor: Uwe Paul Schroeder
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Publication number: 20170293704Abstract: Methodologies and a device for assessing integrated circuit and pattern for yield risk based on 3D simulation of semiconductor patterns are provided. Embodiments include generating, with a processor, a 3D simulation of semiconductor patterns; obtaining critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns; comparing the set of critical dimensions with predefined minimum dimensions; and yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step.Type: ApplicationFiled: April 12, 2016Publication date: October 12, 2017Inventors: Jaime BRAVO, Vikrant CHAUHAN, Piyush PATHAK, Shobhit MALIK, Uwe Paul SCHROEDER
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Patent number: 9547741Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout.Type: GrantFiled: October 20, 2014Date of Patent: January 17, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Uwe Paul Schroeder, Sushama Davar
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Publication number: 20160110489Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout.Type: ApplicationFiled: October 20, 2014Publication date: April 21, 2016Inventors: Uwe Paul Schroeder, Sushama Davar
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Publication number: 20160099239Abstract: At least one method, apparatus and system disclosed herein involves performing power reduction process on a FinFET device. A first design is provided. The first design comprises a process mask definition, a FinFET device that comprises a plurality of fins characterized by said process mask, and a timing requirement relating to an operation of said FinFET device. A timing parameter of said operation of said FinFET device is determined. Based upon said timing parameter, a determination is made as to whether a drive capability of said FinFET device is above a level required to maintain said timing requirement. The process mask is modified for reducing at least one of said fins in response to said determining that said drive capability is above said level required to maintain said timing requirement.Type: ApplicationFiled: December 10, 2015Publication date: April 7, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Uwe Paul Schroeder, Sushama Davar
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Patent number: 9245087Abstract: At least one method, apparatus and system disclosed herein involves performing power reduction process on a FinFET device. A first design is provided. The first design comprises a process mask definition, a FinFET device that comprises a plurality of fins characterized by said process mask, and a timing requirement relating to an operation of said FinFET device. A timing parameter of said operation of said FinFET device is determined. Based upon said timing parameter, a determination is made as to whether a drive capability of said FinFET device is above a level required to maintain said timing requirement. The process mask is modified for reducing at least one of said fins in response to said determining that said drive capability is above said level required to maintain said timing requirement.Type: GrantFiled: August 29, 2014Date of Patent: January 26, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Uwe Paul Schroeder, Sushama Davar
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Patent number: 9195142Abstract: Lithography masks, lithography systems, methods of manufacturing lithography masks, methods of altering material layers of semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a lithography mask includes a first pattern for at least one material layer of at least one die, the first pattern being oriented in a first position. The lithography mask includes a second pattern for at least one material layer of the at least one die, the second pattern being oriented in a second position. The second position is different than the first position.Type: GrantFiled: December 11, 2013Date of Patent: November 24, 2015Assignee: Infineon Technologies AGInventor: Uwe Paul Schroeder
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Publication number: 20150283604Abstract: A casting mold for producing a hollow component having apertures and inner walls is provided, in which the casting mold has at least one inner wall element having apertures, into which liquid metal can also propagate, wherein at least one inner wall element has an end face in the region of the aperture, which end face is beveled and which runs at an angle differing from 90° to a propagation direction of the liquid metal or of side surfaces of the inner wall elements in the casting mold. Accordingly, the propagation front of liquid material in the casting mould is influenced by a specific modification of the end faces of inner wall elements and influences or the formation of oxide layers are displaced to less critical regions of the casting portal to be produced.Type: ApplicationFiled: October 25, 2013Publication date: October 8, 2015Applicant: Siemens AktiengesellschaftInventors: Fathi Ahmad, Uwe Paul
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Patent number: 9068251Abstract: A nickel-based superalloy is provided. Known nickel-based superalloys for producing components made of stem shaped single crystals do not provide sufficiently for grain boundary strength. The superalloy includes a low molybdenum content and very accurately adjusted values for elements having grain boundary strength and elements that precipitate in grain boundaries.Type: GrantFiled: October 20, 2009Date of Patent: June 30, 2015Assignees: SIEMENS AKTIENGESELLSCHAFT, HOWMET CORPORATIONInventors: Winfried Eβer, Dirk Goldschmidt, Christopher R. Hanslits, Michael Ott, Uwe Paul, Ursula Pickert, Russell G. Vogt
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Publication number: 20150017014Abstract: A core (10) for casting a hollow component of a turbomachine. The core includes a first portion (12) for providing a shape to the component and a second portion (14) located outside of the component. The second portion (14) comprises a plurality of indentations (16) for preventing a breakage of the core (10) at a region proximal to the first portion (14).Type: ApplicationFiled: December 18, 2012Publication date: January 15, 2015Inventors: Fathi Ahmad, Uwe Paul
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Patent number: 8853791Abstract: A memory cell includes diffusion regions formed in a substrate. Each of the diffusion regions extends along a vertical direction in a layout view at a substrate level. A first gate electrode structure at a gate electrode level is generally dogleg shaped. The first gate electrode structure extends in an oblique direction, turns to a horizontal direction, extends over and crosses the diffusion regions in the horizontal direction. A first contact structure at a contact level is generally rectangular shaped in the layout view of the cell. The first contact structure electrically connects a first source/drain region of the first diffusion region to the first gate electrode structure and the first source/drain region of the second diffusion region. The first contact structure extends from the first source/drain region of the first diffusion region to the first source/drain region of the second diffusion region at the contact level.Type: GrantFiled: November 6, 2006Date of Patent: October 7, 2014Assignee: Infineon Technologies AGInventors: Uwe Paul Schroeder, Martin Ostermayr