Abstract: A communication device is described including a memory, a receiver configured to receive data via a communication channel and a controller configured to determine whether the communication device is to request a retransmission for the received data, to store the received data in the memory if the communication device is to request a retransmission for the received data and to prevent storing of the received data in the memory if the communication device is to omit a request for a retransmission for the received data.

Abstract: A communication device is described including a memory, a receiver configured to receive data via a communication channel and a controller configured to determine whether the communication device is to request a retransmission for the received data, to store the received data in the memory if the communication device is to request a retransmission for the received data and to prevent storing of the received data in the memory if the communication device is to omit a request for a retransmission for the received data.

Abstract: A hardware accelerator module is driven by a system processor via a system bus to sequentially process data blocks of a data stream as a function of a parameter set defined by the processor. The module includes a register block adapted to receive parameter sets from the system processor, an accelerator core adapted to receive streaming data, to process data blocks of said streaming data in a manner defined by a parameter set, and to output processed streaming data, and a parameter buffering block adapted to consecutively store a plurality of parameter sets and to sequentially provide the parameter sets to the hardware accelerator core as a function of a busy state of the hardware accelerator core. The parameter buffering block enables to reduce downtimes of hardware accelerators, to increase data throughput, and to reduce the risk of a processor overload in a processor which drives several hardware accelerators.

Abstract: A hardware accelerator module is driven by a system processor via a system bus to sequentially process data blocks of a data stream as a function of a parameter set defined by the processor. The module includes a register block adapted to receive parameter sets from the system processor, an accelerator core adapted to receive streaming data, to process data blocks of said streaming data in a manner defined by a parameter set, and to output processed streaming data, and a parameter buffering block adapted to consecutively store a plurality of parameter sets and to sequentially provide the parameter sets to the hardware accelerator core as a function of a busy state of the hardware accelerator core. The parameter buffering block enables to reduce downtimes of hardware accelerators, to increase data throughput, and to reduce the risk of a processor overload in a processor which drives several hardware accelerators.