Abstract: An apparatus and method are described for performing a low overhead error checking and correction. For example, one embodiment of an electronic circuit comprises: one or more memories to store data or instructions in rows and columns, and to further store row parity data comprising a parity value associated with each row and column parity data comprising a parity value associated with each column; and error checking logic to perform a row parity check to detect if errors exist in any of the rows, wherein if an error is detected in one of the rows, the error checking and correction logic is to perform a column parity check to identify a column in which the detected error occurred; and error correction logic to correct the detected error using the detected row and column identified by the error checking logic.

Abstract: The invention relates to a method and a system for synchronizing a debugging process of a multiprocessor system (1) with a number of processors (2.1 to 2.3), comprising the following steps: —if for one of the processors (2.1 to 2.3) a debugging process is requested by a STOP-signal (STOP#2.1 to STOP#2.3) a HALT-signal (HALT#2.1 to HALT#2.3) to the other processors (2.1 to 2.3) is asserted until their STOP-signal (STOP#2.1 to STOP#2.3) for debugging request is asserted to them, —asserting a respective HALT-signal (HALT#2.1 to HALT#2.3) to each processor (2.1 to 2.3) which has finished the debugging process until the other processors (2.1 to 2.3) have finished their respective debugging processeS, —starting all processors (2.1 to 2.3) synchronously after all HALT-signals (HALT#2.1 to HALT#2.3) and/or STOP-signals (STOP#2.1 to STOP#2.3) are de-asserted and all debugging processes are finished.