Abstract: In order to measure a surface profile of a sample, an imprint of the surface profile to be examined is produced in a transfer material. The sample contains processed semiconductor material and is in particular a patterned semiconductor wafer or part of a patterned semiconductor wafer. The transfer material is deformable and curable under suitable ambient conditions. The transfer material may be a thermoplastic material or a material which is deformable as desired after application on a substrate and cures in one case by means of irradiation with photons having a suitable wavelength or alternatively heating. The transfer material may be configured in such a way that the imprint produced is the same size as or alternatively of smaller size than the surface profile. The imprint produced is subsequently measured by known methods.

Abstract: A method for fabricating a trench isolation structure wherein a trench is formed in a silicon body and an oxide layer is formed in the trench. The silicon body is exposed at the bottom of the trench by means of an etching step, and silicon oxide is selectively grown on the silicon exposed at the bottom of the trench, the silicon oxide being grown from the bottom of the trench toward an upper edge of the trench.

Abstract: An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.

Abstract: The present invention relates to a method of forming an isolating trench of a semiconductor device with a dielectric material, and to a method of forming an isolating trench in a memory device.

Abstract: In a method for the reversible oxidation protection of microcomponents, a substrate is provided, a silicon nitride layer is provided on the substrate in order to protect it against oxidation, an insulation layer is applied to the silicon nitride layer, and a reoxidation process is carried out. In the reoxidation process are generated oxygen radicals which are passed through the insulation layer to the silicon nitride layer in order to convert silicon nitride of the nitride layer into silicon dioxide.

Abstract: The present invention relates to a method of forming an isolating trench of a semiconductor device with a dielectric material, and to a method of forming an isolating trench in a memory device.

Abstract: A method of forming a contact to an underlayer of a device includes the steps of forming a contact hole, forming a contact hole barrier layer of a barrier material in the contact hole of the device, etching the contact hole barrier layer on the bottom surface of the contact hole, depositing a liner material in the contact hole, and filling the contact hole with a conductive material. A device such as a semiconductor, passive device, capacitor or FeRAM is formed in accordance with the method. The portions of the contact hole barrier layer on the side walls of the contact hole inhibit lateral diffusion of hydrogen and/or oxygen. The contact hole barrier layer can be performed after a wet etch process to fill voids in an existing barrier layer caused by that process, or prior to the wet etch process to prevent damage to the existing barrier layer.

Abstract: An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.

Abstract: An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.

Abstract: In a method for the reversible oxidation protection of microcomponents, a substrate is provided, a silicon nitride layer is provided on the substrate in order to protect it against oxidation, an insulation layer is applied to the silicon nitride layer, and a reoxidation process is carried out. In the reoxidation process are generated oxygen radicals which are passed through the insulation layer to the silicon nitride layer in order to convert silicon nitride of the nitride layer into silicon dioxide.

Abstract: A method for fabricating a trench isolation structure wherein a trench is formed in a silicon body and an oxide layer is formed in the trench. The silicon body is exposed at the bottom of the trench by means of an etching step, and silicon oxide is selectively grown on the silicon exposed at the bottom of the trench, the silicon oxide being grown from the bottom of the trench toward an upper edge of the trench.

Abstract: A method of oxidizing an object to be processed comprises the steps of: providing an object to be processed W having a groove 4 formed on its surface in a processing vessel 22 capable of forming a vacuum therein, oxidizing the surface of the object to be processed in an atmosphere including active oxygen species and active hydroxyl species which are generated by supplying an oxidative gas and a reductive gas into the processing vessel to interact the gases. A temperature in the processing vessel during the oxidizing step is set to be equal to or less than 900° C. Thus, not only corner portions of shoulders of a trench (groove) but also corner portions of a bottom portion of the trench can be rounded to have curved surfaces so as to prevent a generation of facet.

Abstract: In order to measure a surface profile of a sample, an imprint of the surface profile to be examined is produced in a transfer material. The sample contains processed semiconductor material and is in particular a patterned semiconductor wafer or part of a patterned semiconductor wafer. The transfer material is deformable and curable under suitable ambient conditions. The transfer material may be a thermoplastic material or a material which is deformable as desired after application on a substrate and cures in one case by means of irradiation with photons having a suitable wavelength or alternatively heating. The transfer material may be configured in such a way that the imprint produced is the same size as or alternatively of smaller size than the surface profile. The imprint produced is subsequently measured by known methods.

Abstract: The invention includes a wafer having a poly silicon plug passing through a CP-contact. The poly silicon plug is formed from a relatively heavily doped poly silicon layer and a relatively lightly doped poly silicon layer. The relatively lightly doped poly silicon layer passes through the relatively heavily doped poly silicon layer to extend beyond the relatively heavily doped poly silicon layer towards the surface of the wafer. A barrier layer covers top and side walls of the relatively lightly doped poly silicon layer for reducing oxidation at the surface of the poly silicon plug. The wafer is fabricated by depositing a relatively heavily doped poly silicon layer in a CP-contact, depositing a relatively lightly doped poly silicon layer to pass through the relatively heavily doped poly silicon layer, and depositing a barrier layer to cover top and side walls of the relatively lightly doped poly silicon layer to reduce oxidation at the surface of the poly silicon plug.

Abstract: Reduced radiation damage to an IC feature is disclosed. At least a portion of the feature which is sensitive to radiation is covered by a radiation protection layer. The radiation protection layer protects the feature from being damaged to radiation during, for example, processing of the IC. In one embodiment, the radiation protection layer comprises a noble metal, oxides, alloys, or compounds thereof.

Abstract: An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.

Abstract: A memory cell having capacitor with top and bottom electrodes with a dielectric layer between is described. The bottom electrode is coupled to a first diffusion region of a transistor by a bottom electrode plug. A dielectric layer covers the capacitor. Above the dielectric layer is a first barrier layer. A via is created in the dielectric layer in which a plug is formed to couple to the second diffusion region. The via comprises substantially vertical sidewalls. A second barrier layer lines the sidewalls of the via. A conductive material is then deposited on the substrate, filling the via to form the plug. By providing the first and second barrier layers, the diffusion of hydrogen which can adversely impact the capacitor is reduced, thereby improving the reliability.

Abstract: An IC with memory cells arranged in a chained architecture is disclosed. The top local interconnect between the top capacitor electrodes and active area is achieved by using a strap. The use of a strap eliminates the need for additional metal layer which reduces manufacturing costs. Furthermore, sidewall spacers are used to isolate the strap from the different layers of the capacitors. The use of spacers advantageously enables the strap to be self-aligned.

Abstract: An annealing apparatus comprises a first chamber and a second chamber. A wafer can be located between the chambers, with a first of its surfaces in the first chamber and a second of its surfaces in the second chamber. Different gases are fed to the two chambers, so that, during an annealing step, the components proximate the two chambers are exposed to different gaseous atmospheres. Gas can penetrate from the top and bottom chambers into the wafer, but interdiffusion is blocked by a diffusion blocker layer (e.g. Si3N4) within the wafer (e.g. separating CMOS devices from ferrocapacitor devices). If one of the gases is active in a thermal treatment (e.g. a hydrogen-rich gas for performing a CMOS device fabrication step), then the other gas may be inert, so that certain regions of the wafer are not subjected to the treatment step.

Abstract: A method of forming a contact to an underlayer of a device includes the steps of forming a contact hole, forming a contact hole barrier layer of a barrier material in the contact hole of the device, etching the contact hole barrier layer on the bottom surface of the contact hole, depositing a liner material in the contact hole, and filling the contact hole with a conductive material. A device such as a semiconductor, passive device, capacitor or FeRAM is formed in accordance with the method. The portions of the contact hole barrier layer on the side walls of the contact hole inhibit lateral diffusion of hydrogen and/or oxygen. The contact hole barrier layer can be performed after a wet etch process to fill voids in an existing barrier layer caused by that process, or prior to the wet etch process to prevent damage to the existing barrier layer.