Patents by Inventor Uzi Magini

Uzi Magini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9836567
    Abstract: A method and device for simulating a semiconductor IC is provided, which comprises generating a high level description of the IC, generating a low level description of the IC comprising a plurality of instances describing the operation of the IC, conducting a low level function analysis of the IC based on metrics values associated with the instances, and performing a design optimization scheme. The scheme comprises mapping the metric values of instances describing functional units different from standard cells, to standard cells logically connected to said instances, by dividing each of the instance metrics values between a group of standard cells logically connected to the corresponding instance and adding each resulting portion of said instance metric value to the metric value of each of the group of standard cells, respectively.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 5, 2017
    Assignee: NXP USA, Inc.
    Inventors: Asher Berkovitz, Uzi Magini, Michael Priel
  • Publication number: 20170286587
    Abstract: Methods for generating constraints associated with an integrated circuit design are provided. The method includes identifying, with a processor, a plurality of paths based on a floor-plan data set, each of the paths specifying a first block, a second block, and a first interconnect between the first block and the second block. Cycle time criteria is determined for each of the plurality of paths. A total delay is estimated for each of the plurality of paths based on a block-to-block delay and an in-block delay, wherein the block-to-block delay is based on the interconnect data associated with the first interconnect, and the in-block delay is based on the cell data associated with the first and second blocks.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Applicant: FREESCALE SEMICONDUCTOR INC.
    Inventors: UZI MAGINI, INBAR NEEMAN, ILAN COHEN, ALON DVIR
  • Publication number: 20150242544
    Abstract: A There is proposed a method and device for simulating a semiconductor IC is provided, which comprises generating a high level description of the IC, generating a low level description of the IC comprising a plurality of instances describing the operation of the IC, conducting a low level function analysis of the IC based on metrics values associated with the instances, and performing a design optimization scheme. The scheme comprises mapping the metric values of instances describing functional units different from standard cells, to standard cells logically connected to said instances, by dividing each of the instance metrics values between a group of standard cells logically connected to the corresponding instance and adding each resulting portion of said instance metric value to the metric value of each of the group of standard cells, respectively.
    Type: Application
    Filed: September 14, 2012
    Publication date: August 27, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Asher Berkovitz, Uzi Magini, Michael Priel