Abstract: There is provided a method of computing a camera pose of a digital image, comprising: computing query-regions of a digital image, each query-region maps to training image region(s) of training image(s) by a 2D translation and/or a 2D scaling, each training image associated with a reference camera pose, each query-region associated with a center point and a computed weighted mask that weights the query-region pixels according to computed correlations with the corresponding training image region, mapping cloud points corresponding to pixels of matched training image region(s) to corresponding images pixels of the matched query-regions according to a statistically significant correlation requirement between the center point of the query-region and the matched training image region, and according to the computed weight mask, and computing the camera pose according to an aggregation of the camera poses, and the mapped cloud points and corresponding image pixels of the matched query-regions.

Abstract: There is provided a method of computing a camera pose of a digital image, comprising: computing query-regions of a digital image, each query-region maps to training image region(s) of training image(s) by a 2D translation and/or a 2D scaling, each training image associated with a reference camera pose, each query-region associated with a center point and a computed weighted mask that weights the query-region pixels according to computed correlations with the corresponding training image region, mapping cloud points corresponding to pixels of matched training image region(s) to corresponding images pixels of the matched query-regions according to a statistically significant correlation requirement between the center point of the query-region and the matched training image region, and according to the computed weight mask, and computing the camera pose according to an aggregation of the camera poses, and the mapped cloud points and corresponding image pixels of the matched query-regions.

Abstract: A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.

Abstract: A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.

Abstract: A method for processing a transaction. The method includes receiving validation requests, automatically initiating one or more callbacks to an authorized transactor, and validating one or responses from the authorized transactor. The automatic initiation is in response to the validation requests, and according to pre-selected authorized transactor information. The responses from the authorized transactor are in reply to the callbacks.

Abstract: A method for processing a transaction includes receiving validation requests, automatically initiating one or more callbacks to an authorized transactor, and validating one or responses from the authorized transactor. The automatic initiation is in response to the validation requests, and according to pre-selected authorized transactor information. The responses from the authorized transactor are in reply to the callbacks. The validation is based upon the pre-selected authorized transactor information.

Abstract: A method for determining vectorization configurations in a computer processor architecture, the method including identifying a vectorizable loop in a computer program, identifying a memory access pattern of data required for implementing the loop in the architecture, computing a set of candidate configurations of resources required for vectorizing the data in the architecture, where the computing step includes configuring a vector pointer register of the architecture in support of either of reorder-on-read use and reorder-on-write use of a vector element file of the architecture, selecting one of the candidates in accordance with predefined selection criteria, and implementing the selected vectorization configuration in the architecture.

Abstract: A method and system for providing an item (112) further to a broadcast (101) are provided. A user request (108) with a time of a broadcast (101) of an item or a reference to an item is received by a service provider (110). The request (108) includes an indication of the broadcast channel. The service provider (110) determines the item from the time of the request (108), the location from the request was sent (if needed), and the indication of the broadcast channel. The item (112) is provided to a target device (106) of the user, either directly from an item provider (114) or from the service provider (110).

Abstract: An apparatus and method are provided for updating one or more pluralities of pointers (i.e. one or more vector pointers) which are used for accessing one or more pluralities of data elements (i.e. one or more vector data elements) in a multi-ported memory. A first register file holds the vector pointers, a second register file holds stride data, and a plurality of functional units combine data from the second register file with data from the first register file. The results of combining the data are transferred to the first register file and represent updated vector pointers. Furthermore, a third register file is provided for holding modulus selector data to specify the size of a circular buffer for circular addressing.

Abstract: A digital signal processor (DSP) includes a SIMD-based organization wherein operations are executed on a plurality of single-instruction multiple data (SIMD) datapaths or stages connected in cascade. The functionality and data values at each stage may be different, including a different width (e.g., a different number of bits per value) in each stage. The operands and destination for data in a computational datapath are selected indirectly through vector pointer registers in a vector pointers datapath. Each vector pointer register contains a plurality of pointers into a register file of a computational datapath.

Abstract: A method for determining vectorization configurations in a computer processor architecture, the method including identifying a vectorizable loop in a computer program, identifying a memory access pattern of data required for implementing the loop in the architecture, computing a set of candidate configurations of resources required for vectorizing the data in the architecture, where the computing step includes configuring a vector pointer register of the architecture in support of either of reorder-on-read use and reorder-on-write use of a vector element file of the architecture, selecting one of the candidates in accordance with predefined selection criteria, and implementing the selected vectorization configuration in the architecture.

Abstract: A method for processing a transaction. The method includes receiving validation requests, automatically initiating one or more callbacks to an authorized transactor, and validating one or responses from the authorized transactor. The automatic initiation is in response to the validation requests, and according to pre-selected authorized transactor information. The responses from the authorized transactor are in reply to the callbacks.

Abstract: An apparatus and method are provided for updating one or more pluralities of pointers (i.e. one or more vector pointers) which are used for accessing one or more pluralities of data elements (i.e. one or more vector data elements) in a multi-ported memory. A first register file holds the vector pointers, a second register file holds stride data, and a plurality of functional units combine data from the second register file with data from the first register file. The results of combining the data are transferred to the first register file and represent updated vector pointers. Furthermore, a third register file is provided for holding modulus selector data to specify the size of a circular buffer for circular addressing.

Abstract: A digital signal processor (DSP) includes a SIMD-based organization wherein operations are executed on a plurality of single-instruction multiple data (SIMD) datapaths or stages connected in cascade. The functionality and data values at each stage may be different, including a different width (e.g., a different number of bits per value) in each stage. The operands and destination for data in a computational datapath are selected indirectly through vector pointer registers in a vector pointers datapath. Each vector pointer register contains a plurality of pointers into a register file of a computational datapath.

Abstract: A two's complement multiplier is combined with additional circuit elements to provide a multiplier capable of multiplication of two operands represented in any combination of either two's complement (signed) or unsigned magnitude formats, without increasing the size of the multiplier compared a multiplier for both operands represented in the same format; achieving the additional capability by providing independent inversion control to the partial product elements in the left column and the bottom row of the multiplier array, and controlling the generation of the carry-in signal to the carry propagate adder that performs the final addition of the partial products.

Abstract: An adapter device includes a telephone port, for coupling to a line connector of a telephone, a computer port, for coupling to a communication port of a computer terminal, and a line port, for coupling to a telephone line, which is linked to a telephone network. The device operates in a plurality of operational modes, including at least a first operational mode, in which the circuitry couples the telephone via the line port to the telephone line so as to enable a telephone call to be conducted over the telephone network using the telephone, while the circuitry conveys data regarding the call to the terminal via the computer port, and a second operational mode, in which the circuitry couples the telephone via the computer port to the computer terminal, so that the telephone operates as an audio input/output device of the terminal.

Abstract: A Voice over DSL (VoDSL) solution allows an end user to buy and install off the shelf IAD (Integrated Access Device) devices for DSL (Digital Subscriber Loop) connection without the need for a technician. Each piece of equipment (telephone, facsimile, modem, computer) is provided with its own adapter which connects to the RJ11 wall connector without requiring rewiring the phone lines in the wall. The adapter enables the telephone equipment to be connected to the DSL link digitally and controlled by the IAD.

Abstract: A time-division multiplexing synchronization mechanism employs a 1-bit/frame framing channel with a pattern that repeats every 2 frames. Acquisition and reacquisition of synchronization with such a framing pattern is enabled through the use of an explicit synchronization procedure. With this procedure, initial acquisition of frame synchronization as well as reframing after loss of synchronization are carried out while the transmission channel is carrying only a predefined bit pattern. When the receivers are in synchronization, synchronization is monitored and maintained using a 1-bit/frame framing channel, while the communications link is carrying multiplexed bit streams with the appropriate format.

Abstract: A data processing system is provided for executing multimedia applications which interface with multimedia end devices that consume or produce at least one of (a) real-time and (b) asynchronous streamed data. The data processing system includes a central processing unit for data processing operations including execution of the multimedia application, a digital signal processor for processing data including the streamed data, and a plurality of modular components which cooperate to provide a substantially open architecture.

Abstract: A signal processor is described for sampling rate conversion of a digitally sampled analog signal, the signal processor including an apparatus for generating an output sampled value for each output sampling instant, the output sampled value being equal to the input sampled value at the last input sampling instant if an input sampling instant has not occurred since the last output sampling instant and being calculated as an interpolation of input values at successive input sampling instants if an input sampling instant has occurred since the last output sampling instant. A virtual, analytic A/D-D/A conversion is employed using digital processing to convert from a given sampling rate to an arbitrary desired rate.