Abstract: Plasmonic systems and devices that utilize surface plasmon polaritons (or “plasmons”) for inter-chip and/or intra-chip communications are provided. A plasmonic system includes a microchip that has an integrated circuit module and a plasmonic device configured to interface with the integrated circuit module. The plasmonic device includes a first electrode, a second electrode positioned at a non-contact distance from the first electrode, and a tunneling-junction configured to create a plasmon when a potential difference is created between the first electrode and the second electrode.

Abstract: In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions in the software program in parallel. A plurality of partitioned memory modules are provided and configured to store data for use by the plurality of parallel processors in executing software instructions in parallel. Accordingly, a processor/memory structure is provided that allows serial programs to use quick local serial memories and parallel programs to use partitioned parallel memories. The system may switch between a serial mode and a parallel mode. The system may incorporate pre-fetching commands of several varieties.

Abstract: In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions in the software program in parallel. A plurality of partitioned memory modules are provided and configured to store data for use by the plurality of parallel processors in executing software instructions in parallel. Accordingly, a processor/memory structure is provided that allows serial programs to use quick local serial memories and parallel programs to use partitioned parallel memories. The system may switch between a serial mode and a parallel mode. The system may incorporate pre-fetching commands of several varieties.

Abstract: A multi-chip processor/memory arrangement replacing a large computer chip, includes a number of modules each including processing elements, registers, and/or memories interconnected by an optical interconnection fabric providing an all-to-all interconnection between the chips, so that the memory cells on each chip represent a portion of shared memory. The optical interconnect fabric is responsible for transporting data between the chips while processing elements on each chip dominate processing. Each chip is manufactured in mass production so that the entire processor/memory arrangement is fabricated in an inexpensive and simplified technology process. The optical communication fabric is based on waveguide technology and includes a number of waveguides, the layout of which follows certain constraints. The waveguides can intersect each other in the single plane, or alternatively, a double layer of waveguide structures and bent over approach may be used.

Abstract: Plasmonic systems and devices that utilize surface plasmon polaritons (or “plasmons”) for inter-chip and/or intra-chip communications are provided. A plasmonic system includes a microchip that has an integrated circuit module and a plasmonic device configured to interface with the integrated circuit module. The plasmonic device includes a first electrode, a second electrode positioned at a non-contact distance from the first electrode, and a tunneling-junction configured to create a plasmon when a potential difference is created between the first electrode and the second electrode.

Abstract: A multi-chip processor/memory arrangement replacing a large computer chip, includes a number of modules each including processing elements, registers, and/or memories interconnected by an optical interconnection fabric providing an all-to-all interconnection between the chips, so that the memory cells on each chip represent a portion of shared memory. The optical interconnect fabric is responsible for transporting data between the chips while processing elements on each chip dominate processing. Each chip is manufactured in mass production so that the entire processor/memory arrangement is fabricated in an inexpensive and simplified technology process. The optical communication fabric is based on waveguide technology and includes a number of waveguides, the layout of which follows certain constraints. The waveguides can intersect each other in the single plane, or alternatively, a double layer of waveguide structures and bent over approach may be used.

Abstract: A method for performing prefix sums, by including a prefix sum instruction in the instruction set of a microprocessor. Both general prefix summation, base-zero prefix summation and base-zero suffix summation are included in the scope of the present invention. The prefix sum instruction may be implemented in software, using the instructions of existing instruction sets, or may be implemented in dedicated hardware, for example, as a functional unit of a microprocessor. The hardware implementation is suitable for application to the allocation of computational resources among concurrent tasks. The scope of the present invention includes one such application: guaranteeing conflict-free access to multiple single-ported register files.