Abstract: A three-dimensional VLSI integrated circuit apparatus is disclosed having a plurality of VLSI layers. A first VLSI layer includes a first silicon sublayer coupleable to at least one heat sink, and a first active silicon sublayer having a (first) plurality of photonic receivers (or transceivers); and a second VLSI layer including a second silicon sublayer having a first plurality of microfluidic cooling channels, and a second active silicon sublayer of the plurality of second VLSI sublayers having an interconnection network. Additional VLSI layers may also include a third VLSI layer having a third silicon sublayer having a second plurality of microfluidic cooling channels and a third active silicon sublayer having a (second) plurality of photonic transmitters (or transceivers). Additional VLSI layers may also include a third VLSI layer having microfluidic cooling channels and memory circuits, and a fourth VLSI layer having microfluidic cooling channels and parallel processing circuitry.

Abstract: A three-dimensional VLSI integrated circuit apparatus is disclosed having a plurality of VLSI layers. A first VLSI layer includes a first silicon sublayer coupleable to at least one heat sink, and a first active silicon sublayer having a (first) plurality of photonic receivers (or transceivers); and a second VLSI layer including a second silicon sublayer having a first plurality of microfluidic cooling channels, and a second active silicon sublayer of the plurality of second VLSI sublayers having an interconnection network. Additional VLSI layers may also include a third VLSI layer having a third silicon sublayer having a second plurality of microfluidic cooling channels and a third active silicon sublayer having a (second) plurality of photonic transmitters (or transceivers). Additional VLSI layers may also include a third VLSI layer having microfluidic cooling channels and memory circuits, and a fourth VLSI layer having microfluidic cooling channels and parallel processing circuitry.

Abstract: In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions in the software program in parallel. A plurality of partitioned memory modules are provided and configured to store data for use by the plurality of parallel processors in executing software instructions in parallel. Accordingly, a processor/memory structure is provided that allows serial programs to use quick local serial memories and parallel programs to use partitioned parallel memories. The system may switch between a serial mode and a parallel mode. The system may incorporate pre-fetching commands of several varieties.

Abstract: In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions in the software program in parallel. A plurality of partitioned memory modules are provided and configured to store data for use by the plurality of parallel processors in executing software instructions in parallel. Accordingly, a processor/memory structure is provided that allows serial programs to use quick local serial memories and parallel programs to use partitioned parallel memories. The system may switch between a serial mode and a parallel mode. The system may incorporate pre-fetching commands of several varieties.

Abstract: The invention presents a unique computational paradigm that provides the tools to take advantage of the parallelism inherent in parallel algorithms to the full spectrum from algorithms through architecture to implementation. The invention provides a new processing architecture that extends the standard instruction set of the conventional uniprocessor architecture. The architecture used to implement this new computational paradigm includes a thread control unit (34), a spawn control unit (38), and an enabled instruction memory (50). The architecture initiates multiple threads and executes them in parallel. Control of the threads is provided such that the threads may be suspended or allowed to execute each at its own pace.

Abstract: The invention relates to an interconnect, and to interconnect architecture, for communicating between processing elements and memory modules in a computer system comprising on-chip parallel computation, in order to reduce the tight synchrony that is required by important components of most present computers.

Abstract: The invention presents a unique computational paradigm that provides the tools to take advantage of the parallelism inherent in parallel algorithms to the full spectrum from algorithms through architecture to implementation. The invention provides a new processing architecture that extends the standard instruction set of the conventional uniprocessor architecture. The architecture used to implement this new computational paradigm includes a thread control unit (34), a spawn control unit (38), and an enabled instruction memory (50). The architecture initiates multiple threads and executes them in parallel. Control of the threads is provided such that the threads may be suspended or allowed to execute each at its own pace.

Abstract: The invention relates to an interconnect, and to interconnect architecture, for communicating between processing elements and memory modules in a computer system comprising on-chip parallel computation, in order to reduce the tight synchrony that is required by important components of most present computers.

Abstract: The invention presents a unique computational paradigm that provides the tools to take advantage of the parallelism inherent in parallel algorithms to the full spectrum from algorithms through architecture to implementation. The invention provides a new processing architecture that extends the standard instruction set of the conventional uniprocessor architecture. The architecture used to implement this new computational paradigm includes a thread control unit (34), a spawn control unit (30), and an enabled instruction memory (50). The architecture initiates multiple threads and executes them in parallel. Control of the threads is provided such that the threads may be suspended or allowed to execute each at its own pace.