Patents by Inventor V. Fuenzalida

V. Fuenzalida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Intermediate structures in porous substrates in which electrical and optical microdevices are fabricated and intermediate structures formed by the same
    Publication number: 20020068369
    Abstract: The invention is a method of fabricating electrically passive components or optical elements on top or underneath of an integrated circuit by using a porous substrate that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. The invention is directed to a method of fabricating electrically passive components like inductors, capacitors, interconnects and resistors or optical elements like light emitters, waveguides, optical switches of filters on top or underneath of an integrated circuit by using porous material layer that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. In the illustrated embodiment the fabrication of voluminous, solenoid-type inductive elements in a porous insulating material by standard back- and front-side-lithography and contacting these two layers by electroplating micro-vias through the pores is described.
    Type: Application
    Filed: August 31, 2001
    Publication date: June 6, 2002
    Inventors: Axel Scherer, Theodore Doll, V. Fuenzalida
  • Method of forming intermediate structures in porous substrates in which electrical and optical microdevices are fabricated and intermediate structures formed by the same
    Patent number: 6350623
    Abstract: The invention is a method of fabricating electrically passive components or optical elements on top or underneath of an integrated circuit by using a porous substrate that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. The invention is directed to a method of fabricating electrically passive components like inductors, capacitors, interconnects and resistors or optical elements like light emitters, waveguides, optical switches of filters on top or underneath of an integrated circuit by using porous material layer that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. In the illustrated embodiment the fabrication of voluminous, solenoid-type inductive elements in a porous insulating material by standard back- and front-side-lithography and contacting these two layers by electroplating micro-vias through the pores is described.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: February 26, 2002
    Assignee: California Institute of Technology
    Inventors: Axel Scherer, Theodore Doll, V. Fuenzalida