Patents by Inventor V. Krishnan

V. Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10211045
    Abstract: An insulator is formed by flowable chemical vapor deposition (FCVD) process. The insulator is cured by exposing the insulator to ultraviolet light while flowing ozone over the insulator to produce a cured insulator. The curing process forms nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters in the insulator. Following the curing process, these methods select wavelengths of microwave radiation (that will be subsequently used during annealing) so that such wavelengths excite the nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters. Then, these methods anneal the cured insulator by exposing the cured insulator to microwave radiation in an inert (e.g., non-oxidizing) ambient atmosphere, at a temperature below 500° C., so as to increase the density of the cured insulator.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: February 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Rishikesh Krishnan, Joseph K. Kassim, Bharat V. Krishnan, Joseph F. Shepard, Jr., Rinus Tek Po Lee, Yiheng Xu
  • Patent number: 10134876
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 20, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bharat V. Krishnan, Timothy J. McArdle, Rinus Tek Po Lee, Shishir K. Ray, Akshey Sehgal
  • Patent number: 10121706
    Abstract: One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from between insulator pillars to expose a portion of a substrate between each insulator pillar, the substrate having a first device region and a second device region; forming a first material over the exposed portions of the substrate between each insulator pillar, the first material including a two-dimensional material; forming a second material over the first material in the first device region, the second material including a first three-dimensional bonding material; and forming a third material over the exposed first material in the second device region, the third material including a second three-dimensional bonding material.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Rinus T. P. Lee, Bharat V. Krishnan, Hui Zang, Matthew W. Stoker
  • Publication number: 20180286982
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Bharat V. KRISHNAN, Timothy J. MCARDLE, Rinus Tek Po LEE, Shishir K. Ray, Akshey SEHGAL
  • Publication number: 20180247936
    Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.
    Type: Application
    Filed: February 27, 2017
    Publication date: August 30, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: SHISHIR K. RAY, BHARAT V. KRISHNAN, JINPING LIU, MEERA S. MOHAN, JOSEPH K. KASSIM
  • Patent number: 10062692
    Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 28, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shishir K. Ray, Bharat V. Krishnan, Jinping Liu, Meera S. Mohan, Joseph K. Kassim
  • Publication number: 20180151449
    Abstract: One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from between insulator pillars to expose a portion of a substrate between each insulator pillar, the substrate having a first device region and a second device region; forming a first material over the exposed portions of the substrate between each insulator pillar, the first material including a two-dimensional material; forming a second material over the first material in the first device region, the second material including a first three-dimensional bonding material; and forming a third material over the exposed first material in the second device region, the third material including a second three-dimensional bonding material.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Inventors: Rinus T. P. Lee, Bharat V. Krishnan, Hui Zang, Matthew W. Stoker
  • Publication number: 20170068984
    Abstract: Offers are provided to consumers by a service on behalf of merchants in response to purchases by the consumer at the merchant, a collaborating merchant, or self-issued from a web site. Offers may be cloned by a consumer and provided to another user. Points may be assigned to consumers and used to purchase offers. Offers are generated with custom parameters for each customer. Offer parameters (e.g., duration, price, benefit) may be varied over time to determine successful parameters that are likely to result in offer redemption. Merchants may collaborate such that issuance of an offer for a first merchant results in issuance by the service of an offer for a second merchant. A fee may be charged by the service to the first merchant with at least a portion of the fee being paid to the second merchant.
    Type: Application
    Filed: September 6, 2016
    Publication date: March 9, 2017
    Inventors: Sunil Pradeep Joshi, Kalyan V. Krishnan
  • Publication number: 20170033181
    Abstract: One illustrative method disclosed herein includes, among other things, individually forming alternating layers of different semiconductor materials in a substrate fin cavity so as to form a multi-layer fin above a recessed substrate fin, wherein each of the layers of different semiconductor materials is formed to a final thickness that is less than a critical thickness of the layer of different semiconductor material being formed, recessing the layer of insulating material so as to expose at least a portion of the multi-layer fin above a recessed upper surface of the layer of insulating material and forming a gate structure around at least a portion of the of exposed the multi-layer fin.
    Type: Application
    Filed: July 28, 2015
    Publication date: February 2, 2017
    Inventors: Timothy J. McArdle, Judson R. Holt, Bharat V. Krishnan, Jody A. Fronheiser
  • Publication number: 20160343024
    Abstract: Transaction parameters for a transaction between a customer and a merchant are provided to a reward service executing on a server system. The reward service assigns zero or more punches to the customer according to the transaction parameters based on legibility rules received from the merchant. The reward service further assigns a cash or points reward to the customer if punches assigned to the customer meet a threshold condition received by the reward service from the merchant. The reward may be assigned according to a tier of the customer, where the tier of the customer increases with a number of times the customer has met previously met the threshold condition. Punches may be provided to the customer as token including a token. The customer may then claim the token in order to associate the punch with the customer.
    Type: Application
    Filed: May 20, 2016
    Publication date: November 24, 2016
    Inventors: Sunil Pradeep Joshi, Kalyan V. Krishnan
  • Publication number: 20160343016
    Abstract: Transaction parameters for a transaction between a customer and a merchant are provided to a reward service executing on a server system. The reward service assigns zero or more punches to the customer according to the transaction parameters based on legibility rules received from the merchant. The reward service further assigns a cash or points reward to the customer if punches assigned to the customer meet a threshold condition received by the reward service from the merchant. The reward may be assigned according to a tier of the customer, where the tier of the customer increases with a number of times the customer has met previously met the threshold condition. Punches may be provided to the customer as token including a token. The customer may then claim the token in order to associate the punch with the customer.
    Type: Application
    Filed: May 18, 2016
    Publication date: November 24, 2016
    Inventors: Sunil Pradeep Joshi, Kalyan V. Krishnan
  • Publication number: 20160150078
    Abstract: Example communication systems and methods are described. In one implementation, a method receives a first message from a user and extracts a user identity and a transaction request. An alias identity is assigned to the user identity. A second message is transmitted to a merchant device in which the second message includes the alias identity and the transaction request. The method receives a third message from the merchant device and extracts the alias identity and a transaction completion confirmation from the third message. A fourth message, which includes the transaction completion confirmation, is communicated to the user based on the user identity.
    Type: Application
    Filed: November 25, 2015
    Publication date: May 26, 2016
    Inventors: Sunil Pradeep Joshi, Kalyan V. Krishnan
  • Publication number: 20160042383
    Abstract: Example customer reward systems and methods are described. In one implementation, a method receives, through a merchant device, data associated with a purchase transaction by a customer such that the data is entered into the merchant device by a user with knowledge of the transaction. The method determines a customer reward associated with the purchase transaction based on the received data entered by the user with knowledge of the transaction. The customer reward is communicated to a server that maintains a customer reward account associated with the customer. The server is instructed to apply the customer reward to the customer reward account associated with the customer.
    Type: Application
    Filed: August 7, 2015
    Publication date: February 11, 2016
    Inventors: Sunil Pradeep Joshi, Kalyan V. Krishnan
  • Publication number: 20150214369
    Abstract: One illustrative device disclosed herein includes a fin defined in a semiconductor substrate having a crystalline structure, wherein at least a sidewall of the fin is positioned substantially in a <100> crystallographic direction of the substrate, a gate structure positioned around the fin, an outermost sidewall spacer positioned adjacent opposite sides of the gate structure, and an epi semiconductor material formed around portions of the fin positioned laterally outside of the outermost sidewall spacers in the source/drain regions of the device, wherein the epi semiconductor material has a substantially uniform thickness along the sidewalls of the fin.
    Type: Application
    Filed: January 27, 2014
    Publication date: July 30, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jody A. Fronheiser, Bharat V. Krishnan, Murat Kerem Akarvardar, Steven Bentley, Ajey Poovannummoottil Jacob, Jinping Liu
  • Publication number: 20150214345
    Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) are provided. Specifically, the device comprises a gate structure formed over a substrate, a source and drain (S/D) embedded within the substrate adjacent the gate structure, and a liner layer (e.g., silicon-carbon) between the S/D and the substrate. In one approach, the liner layer is formed atop the S/D as well. As such, the liner layer formed in the junction prevents dopant diffusion from the source/drain.
    Type: Application
    Filed: January 27, 2014
    Publication date: July 30, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jing Wan, Jinping Liu, Churamani Gaire, Mariappan Hariharaputhiran, Andy Chih-Hung Wei, Bharat V. Krishnan, Cuiqin Xu, Michael Ganz
  • Publication number: 20150097197
    Abstract: Embodiments of the present invention provide an improved finFET and methods of fabrication. A sigma cavity is used with an n-type finFET to allow multiple epitaxial layers to be disposed adjacent to a finFET gate. In some embodiments, stacking faults may be formed in the epitaxial layers using a stress memorization technique.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Michael Ganz, Johannes M. van Meer, Bharat V. Krishnan
  • Patent number: 8912085
    Abstract: A methodology for enabling a gate stack integration process that provides additional threshold voltage margin without sacrificing gate reliability and the resulting device are disclosed. Embodiments include conformally forming a margin adjusting layer in a gate trench, forming a metal capping layer on the margin adjusting layer, and forming an n-type work function (nWF) metal layer on the metal capping layer.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: December 16, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Bongki Lee, Bharat V. Krishnan, Jinping Liu
  • Publication number: 20140070358
    Abstract: A methodology is disclosed enabling the formation of silicon trench profiles for devices, such as SSRW FETs, having a resultant profile that enables desirable epitaxial growth of semiconductor materials. Embodiments include forming a trench in a silicon wafer between STI regions, thermally treating the silicon surfaces of the trench, and forming Si:C in the trench. The process eliminates a need for an isotropic silicon etch to achieve a desirable flat surface. Further, the flat bottom surface provides a desirable surface for epitaxial growth of semiconductor materials, such as Si:C.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Yi Qi, Puneet Khanna, Srikanth Samavedam, Vara G. Vakada, Michael P. Ganz, Sri Charan Vemula, Laegu Kang, Bharat V. Krishnan
  • Publication number: 20130066199
    Abstract: Systems and methods for detecting tumor margins are disclosed. The detection can be performed intra-operatively. A device is provided for housing a tissue sample during optical analysis for detection of tumor margins.
    Type: Application
    Filed: April 15, 2011
    Publication date: March 14, 2013
    Applicant: CEDARS-SINAI MEDICAL CENTER
    Inventor: V Krishnan Ramanujan
  • Publication number: 20120302805
    Abstract: The present subject matter relates to a feed nozzle assembly 100 for atomizing a heavy hydrocarbon feed by mixing the hydrocarbon feed with a diluent and an atomizing media. The feed nozzle assembly 100 includes at least one primary mixing chambers 101 for receiving the liquid hydrocarbon feed and the diluent to create a primary mixture. The primary mixture is than forwarded to a secondary mixing chamber 102. The secondary mixing chamber extends to a tertiary mixing chamber 103. A steam inlet 110 is provided to inject streams of steam to the secondary mixing chamber 102 and to the tertiary mixing chamber 103 through a first opening and a second opening, respectively, located within the steam inlet 110.
    Type: Application
    Filed: December 3, 2010
    Publication date: November 29, 2012
    Inventors: Bidyut De, P.K. Kasliwal, D. Bhattacharyya, V. Krishnan, S. Rajagopal