Abstract: A variable gain amplifier having an input node, a variable current source including a control input coupled to the input node, first and second branches coupled in parallel between a first supply terminal and the variable current source, the first and second branches defining a differential pair arranged to be controlled by first and second differential gain signals and having first and second output terminals, one of the output terminals including an output node of the variable gain amplifier; and a potential divider having a middle node coupled to the first and second output terminals, wherein the middle node is also coupled to the input node by a capacitor.

Abstract: A variable gain amplifier having an input node, a variable current source including a control input coupled to the input node, first and second branches coupled in parallel between a first supply terminal and the variable current source, the first and second branches defining a differential pair arranged to be controlled by first and second differential gain signals and having first and second output terminals, one of the output terminals including an output node of the variable gain amplifier; and a potential divider having a middle node coupled to the first and second output terminals, wherein the middle node is also coupled to the input node by a capacitor.

Abstract: A variable gain amplifier having an input node, a variable current source including a control input coupled to the input node, first and second branches coupled in parallel between a first supply terminal and the variable current source, the first and second branches defining a differential pair arranged to be controlled by first and second differential gain signals and having first and second output terminals, one of the output terminals including an output node of the variable gain amplifier; and a potential divider having a middle node coupled to the first and second output terminals, wherein the middle node is also coupled to the input node by a capacitor.

Abstract: The present invention relates to a method of implementing an intermetallic capacitor in a multiple layer integrated circuit including, on a P-type substrate, at least five levels of metallization. The method includes letting remain, on either side of portions of end metallization levels of the capacitor, at least one portion of a biasable level distinct from the substrate and from the last metallization level, and biasing, at least above the capacitor and to the potential of the substrate, the two biasable portions.