Patents by Inventor V. Swaminathan
V. Swaminathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200158782Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.Type: ApplicationFiled: April 30, 2019Publication date: May 21, 2020Inventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Yazhou Zu
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Patent number: 10635490Abstract: An aspect includes optimizing an application workflow. The optimizing includes characterizing the application workflow by determining at least one baseline metric related to an operational control knob of an embedded system processor. The application workflow performs a real-time computational task encountered by at least one mobile embedded system of a wirelessly connected cluster of systems supported by a server system. The optimizing of the application workflow further includes performing an optimization operation on the at least one baseline metric of the application workflow while satisfying at least one runtime constraint. An annotated workflow that is the result of performing the optimization operation is output.Type: GrantFiled: November 24, 2015Date of Patent: April 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ramon Bertran Monfort, Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Hans M. Jacobson, William J. Song, Karthik V. Swaminathan, Augusto J. Vega, Liang Wang
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Patent number: 10607715Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.Type: GrantFiled: June 13, 2017Date of Patent: March 31, 2020Assignee: International Business Machines CorporationInventors: Alper Buyuktosunoglu, Swagath Venkataramani, Rajiv Joshi, Karthik V. Swaminathan, Schuyler Eldridge, Pradip Bose
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Patent number: 10365327Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.Type: GrantFiled: October 18, 2017Date of Patent: July 30, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Yazhou Zu
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Publication number: 20190164048Abstract: A system includes a determination component that determines output for successively larger neural networks of a set; and a consensus component that determines consensus between a first neural network and a second neural network of the set. A linear chain of increasingly complex neural networks trained on progressively larger inputs is utilized (e.g., increasingly complex neural networks is generally representative of increased accuracy). Outputs of progressively networks are computed until a consensus point is reached—where two or more successive large networks yield a same inference output. At such point of consensus the larger neural network of the set reaching consensus can be deemed appropriately sized (or of sufficient complexity) for a classification task at hand.Type: ApplicationFiled: November 29, 2017Publication date: May 30, 2019Inventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Swagath Venkataramani
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Publication number: 20190138903Abstract: An N modular redundancy method, system, and computer program product include a computer-implemented N modular redundancy method for neural networks, the method including selectively replicating the neural network by employing one of checker neural networks and selective N modular redundancy (N-MR) applied only to critical computations.Type: ApplicationFiled: November 8, 2017Publication date: May 9, 2019Inventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V Swaminathan, Augusto Vega, Swagath Venkataramani
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Publication number: 20190113572Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.Type: ApplicationFiled: October 18, 2017Publication date: April 18, 2019Inventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Yazhou Zu
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Publication number: 20180358110Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.Type: ApplicationFiled: June 13, 2017Publication date: December 13, 2018Inventors: Alper Buyuktosunoglu, Swagath Venkataramani, Rajiv Joshi, Karthik V. Swaminathan, Schuyler Eldridge, Pradip Bose
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Patent number: 9801565Abstract: In a breast imaging method, magnetic resonance data are acquired of one or both breasts of a subject (16) using a breast coil (20, 20?) coupled with said one or both breasts. The acquiring employs at least four independent channels (41, 42, 43, 44, 45, 46; 61, 62, 63, 64, 65, 66) per breast. The acquired magnetic resonance data are processed to generate at least one of (i) an image, (ii) a spectrum, and (iii) elasticity data. The at least four independent channels per breast are suitably embodied as a dual breast coil (20) including left breast conductors (31, 32, 33, 34, 35, 36) defining at least four independent left breast acquisition channels (41, 42, 43, 44, 45, 46) and right breast conductors (51, 52, 53, 54, 55, 56) defining at least four independent right breast acquisition channels (61, 62, 63, 64, 65, 66).Type: GrantFiled: January 8, 2007Date of Patent: October 31, 2017Assignee: Koninklijke Philips N.V.Inventor: Srirama V. Swaminathan
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Patent number: 9690555Abstract: An aspect includes optimizing an application workflow. The optimizing includes characterizing the application workflow by determining at least one baseline metric related to an operational control knob of an embedded system processor. The application workflow performs a real-time computational task encountered by at least one mobile embedded system of a wirelessly connected cluster of systems supported by a server system. The optimizing of the application workflow further includes performing an optimization operation on the at least one baseline metric of the application workflow while satisfying at least one runtime constraint. An annotated workflow that is the result of performing the optimization operation is output.Type: GrantFiled: June 29, 2015Date of Patent: June 27, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ramon Bertran Monfort, Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Hans M. Jacobson, William J. Song, Karthik V. Swaminathan, Augusto J. Vega, Liang Wang
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Publication number: 20170068521Abstract: An aspect includes optimizing an application workflow. The optimizing includes characterizing the application workflow by determining at least one baseline metric related to an operational control knob of an embedded system processor. The application workflow performs a real-time computational task encountered by at least one mobile embedded system of a wirelessly connected cluster of systems supported by a server system. The optimizing of the application workflow further includes performing an optimization operation on the at least one baseline metric of the application workflow while satisfying at least one runtime constraint. An annotated workflow that is the result of performing the optimization operation is output.Type: ApplicationFiled: June 29, 2015Publication date: March 9, 2017Inventors: Ramon Bertran Monfort, Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Hans M. Jacobson, William J. Song, Karthik V. Swaminathan, Augusto J. Vega, Liang Wang
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Publication number: 20160378550Abstract: An aspect includes optimizing an application workflow. The optimizing includes characterizing the application workflow by determining at least one baseline metric related to an operational control knob of an embedded system processor. The application workflow performs a real-time computational task encountered by at least one mobile embedded system of a wirelessly connected cluster of systems supported by a server system. The optimizing of the application workflow further includes performing an optimization operation on the at least one baseline metric of the application workflow while satisfying at least one runtime constraint. An annotated workflow that is the result of performing the optimization operation is output.Type: ApplicationFiled: November 24, 2015Publication date: December 29, 2016Inventors: Ramon Bertran Monfort, Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Hans M. Jacobson, William J. Song, Karthik V. Swaminathan, Augusto J. Vega, Liang Wang
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Patent number: 9424308Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.Type: GrantFiled: March 7, 2016Date of Patent: August 23, 2016Assignee: International Business Machines CorporationInventors: Alper Buyuktosunoglu, Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan
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Patent number: 9396143Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.Type: GrantFiled: December 4, 2015Date of Patent: July 19, 2016Assignee: International Business Machines CorporationInventors: Alper Buyuktosunoglu, Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan
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Publication number: 20160171045Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.Type: ApplicationFiled: March 7, 2016Publication date: June 16, 2016Inventors: Alper Buyuktosunoglu, Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan
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Publication number: 20160085702Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.Type: ApplicationFiled: December 4, 2015Publication date: March 24, 2016Inventors: Alper Buyuktosunoglu, Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan
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Patent number: 9268863Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.Type: GrantFiled: June 3, 2014Date of Patent: February 23, 2016Assignee: International Business Machines CorporationInventors: Alper Buyuktosunoglu, Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan
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Publication number: 20150347592Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.Type: ApplicationFiled: June 3, 2014Publication date: December 3, 2015Applicant: International Business Machines CorporationInventors: Alper Buyuktosunoglu, Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan
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Patent number: 8661037Abstract: A system and method for indexing documents in a data storage system includes generating a single document hash table in storage memory for a single document using an index construction in a multithreaded and scalable configuration wherein multiple threads are each assigned work to reduce synchronization between threads. The single document hash table includes partitioning the single document and indexing strings of partitioned portions of the single document to create a minor hash table for each document sub-part; generating a document level hash table from the minor hash tables; updating a stream level hash table for the strings which maps every string to a global identifier; and generating a term reordered array from the document level hash table.Type: GrantFiled: April 9, 2010Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Ankur Narang, Karthik V. Swaminathan, Prashant Agrawal, Doug Joseph
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Publication number: 20110252033Abstract: A system and method for indexing documents in a data storage system includes generating a single document hash table in storage memory for a single document using an index construction in a multithreaded and scalable configuration wherein multiple threads are each assigned work to reduce synchronization between threads. The single document hash table includes partitioning the single document and indexing strings of partitioned portions of the single document to create a minor hash table for each document sub-part; generating a document level hash table from the minor hash tables; updating a stream level hash table for the strings which maps every string to a global identifier; and generating a term reordered array from the document level hash table.Type: ApplicationFiled: April 9, 2010Publication date: October 13, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: ANKUR NARANG, Karthik V. Swaminathan, Prashant Agrawal, Doug Joseph