Patents by Inventor V. Veeresh Babu

V. Veeresh Babu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cell balancing module and method in voltage balancing device for a stack of batteries which compares the cell voltages to a coded reference voltage derived from at least two reference voltages
    Patent number: 9647463
    Abstract: The invention relates to a cell balancing module, particularly for voltage balancing of a stack of batteries. The cell balancing module comprises an interface (SPI, VrefH, VrefL) to input a coded reference voltage (Vref) and input nodes (In1, . . . , InN) for connecting a stack of energy storage cells (BAT1, . . . , BATn). A switching unit (SW) is connected to each of the input nodes (In1, . . . , InN) and a local balancing unit (loc) coupled to the switching unit (SW) and the interface (SPI, VrefH, VrefL). The local balancing unit (loc) is designed to compare the coded reference voltage (Vref) with cell voltages (VBAT1, . . . , VBATn) of the stack of energy storage cells (BAT1, . . . , BATn) to be connected and to charge balance the stack of energy storage cells (BAT1, . . . , BATn) to be connected depending on the comparison of coded reference voltage (Vref) and cell voltages (VBAT1, . . . , VBATn).
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: May 9, 2017
    Assignee: AMS AG
    Inventors: Manfred Brandl, Sandeep Vernekar, Vijay Ele, Sudhakar Singamala, V. Veeresh Babu
  • CELL BALANCING MODULE, VOLTAGE BALANCER DEVICE, AND METHOD FOR VOLTAGE BALANCING, PARTICULARLY FOR VOLTAGE BALANCING OF A STACK OF BATTERIES
    Publication number: 20140035532
    Abstract: The invention relates to a cell balancing module, particularly for voltage balancing of a stack of batteries. The cell balancing module comprises an interface (SPI, VrefH, VrefL) to input a coded reference voltage (Vref) and input nodes (In1, . . . , InN) for connecting a stack of energy storage cells (BAT1, . . . , BATn). A switching unit (SW) is connected to each of the input nodes (In1, . . . , InN) and a local balancing unit (loc) coupled to the switching unit (SW) and the interface (SPI, VrefH, VrefL). The local balancing unit (loc) is designed to compare the coded reference voltage (Vref) with cell voltages (VBAT1, . . . , VBATn) of the stack of energy storage cells (BAT1, . . . , BATn) to be connected and to charge balance the stack of energy storage cells (BAT1, . . . , BATn) to be connected depending on the comparison of coded reference voltage (Vref) and cell voltages (VBAT1, . . . , VBATn).
    Type: Application
    Filed: February 14, 2012
    Publication date: February 6, 2014
    Applicant: AMS AG
    Inventors: Manfred Brandl, Sandeep Vernekar, Vijay Ele, Sudhakar Singamala, V. Veeresh Babu