Patents by Inventor V. Visvanathan

V. Visvanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120167031
    Abstract: A method of designing a semiconductor device includes preparing a first design for a semiconductor device and estimating leakage current for the first design. The method also includes determining a leakage current cumulative distribution function (CDF) for the first design. The method further includes preparing a second design for the semiconductor device based on determination of the leakage current CDF for the first design. Further, the method includes estimating leakage current for the second design. The method also includes determining a leakage current CDF for the second design in accordance to the determination of the leakage current CDF for the first design. Moreover, the method includes selecting one of the first design and the second design based on a comparison of the leakage current CDF for the first design and the leakage CDF for the second design.
    Type: Application
    Filed: December 28, 2010
    Publication date: June 28, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Palkesh Jain, Ajoy Mandal, Arvind NV, V. Visvanathan
  • Patent number: 6560568
    Abstract: A production process is used to mass-produce chips, each chip being formed in a substrate of a wafer and having an integrated circuit, each integrated circuit having a plurality of primitive device model types. The integrated circuits are produced using a statistical device model for the production process, which is derived from the sets of e-test data.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: May 6, 2003
    Assignee: Agere Systems, Inc.
    Inventors: Kumud Singhal, V. Visvanathan
  • Patent number: 6356861
    Abstract: A set of worst-case device model files is provided for a production process used to mass-produce integrated circuits having a plurality of primitive device model types. A statistical device model for the production process is derived directly from the worst-case files.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: March 12, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Kumud Singhal, V. Visvanathan