Abstract: Pin probes and pin probe arrays are provided that allow electric contact to be made with selected electronic circuit components. Some embodiments include one or more compliant pin elements located within a sheath. Some embodiments include pin probes that include locking or latching elements that may be used to fix pin portions of probes into sheaths. Some embodiments provide for fabrication of probes using multi-layer electrochemical fabrication methods.

Abstract: In some embodiments, multilayer structures are electrochemically fabricated from at least one structural material (e.g. nickel), at least one sacrificial material (e.g. copper), and at least one sealing material (e.g. solder). In some embodiments, the layered structure is made to have a desired configuration which is at least partially and immediately surrounded by sacrificial material which is in turn surrounded almost entirely by structural material. The surrounding structural material includes openings in the surface through which etchant can attack and remove trapped sacrificial material found within. Sealing material is located near the openings. After removal of the sacrificial material, the box is evacuated or filled with a desired gas or liquid. Thereafter, the sealing material is made to flow, seal the openings, and resolidify. In other embodiments, a post-layer formation lid or other enclosure completing structure is added.

Abstract: In some embodiments, multilayer structures are electrochemically fabricated from at least one structural material (e.g. nickel), at least one sacrificial material (e.g. copper), and at least one sealing material (e.g. solder). In some embodiments, the layered structure is made to have a desired configuration which is at least partially and immediately surrounded by sacrificial material which is in turn surrounded almost entirely by structural material. The surrounding structural material includes openings in the surface through which etchant can attack and remove trapped sacrificial material found within. Sealing material is located near the openings. After removal of the sacrificial material, the box is evacuated or filled with a desired gas or liquid. Thereafter, the sealing material is made to flow, seal the openings, and resolidify. In other embodiments, a post-layer formation lid or other enclosure completing structure is added.

Abstract: Embodiments of the present invention are directed to the formation of microprobe tips elements having a variety of configurations. In some embodiments tips are formed from the same building material as the probes themselves, while in other embodiments the tips may be formed from a different material and/or may include a coating material. In some embodiments, the tips are formed before the main portions of the probes and the tips are formed in proximity to or in contact with a temporary substrate.

Abstract: Multilayer probe structures for testing or otherwise making electrical contact with semiconductor die or other electronic components are electrochemically fabricated via depositions of one or more materials in a plurality of overlaying and adhered layers. In some embodiments the structures may include configurations intended to enhance functionality, buildability, or both.

Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Abstract: Embodiments of the invention provide methods for packaging integrated circuits and/or other electronic components with electrochemically fabricated structures which include conductive interconnection elements. In some embodiments the electrochemically produced structures are fabricated on substrates that include conductive vias while in other embodiments, the substrates are solid blocks of conductive material, or conductive material containing passages that allow the flow of fluid to maintain desired thermal properties of the packaged electronic components.

Abstract: Embodiments of the present invention are directed to the formation of microprobe tips elements having a variety of configurations. In some embodiments tips are formed from the same building material as the probes themselves, while in other embodiments the tips may be formed from a different material and/or may include a coating material. In some embodiments, the tips are formed before the main portions of the probes and the tips are formed in proximity to or in contact with a temporary substrate.

Abstract: Multilayer test probe structures are electrochemically fabricated via depositions of one or more materials in a plurality of overlaying and adhered layers. In some embodiments each probe structure may include a plurality of contact arms or contact tips that are used for contacting a specific pad or plurality of pads wherein the arms and/or tips are configured in such away so as to provide a scrubbing motion (e.g. a motion perpendicular to a primary relative movement motion between a probe carrier and the IC) as the probe element or array is made to contact an IC, or the like, and particularly when the motion between the probe or probes and the IC occurs primarily in a direction that is perpendicular to a plane of a surface of the IC. In some embodiments arrays of multiple probes are provided and even formed in desired relative position simultaneously.

Abstract: Embodiments of invention are directed to the formation of microprobes (i.e. compliant electrical or electronic contact elements) on a temporary substrate, dicing individual probe arrays, and then transferring the arrays to space transformers or other permanent substrates. Some embodiments of the invention transfer probes to permanent substrates prior to separating the probes from a temporary substrate on which the probes were formed while other embodiments do the opposite. Some embodiments, remove sacrificial material prior to transfer while other embodiments remove sacrificial material after transfer. Some embodiments are directed to the bonding of first and second electric components together using one or more solder bumps with enhanced aspect ratios (i.e. height to width ratios) obtained as a result of surrounding the bumps at least in part with rings of a retention material. The retention material may act be a solder mask material.

Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Abstract: Embodiments of the present invention are directed to the formation of microprobe tips elements having a variety of configurations. In some embodiments tips are formed from the same building material as the probes themselves, while in other embodiments the tips may be formed from a different material and/or may include a coating material. In some embodiments, the tips are formed before the main portions of the probes and the tips are formed in proximity to or in contact with a temporary substrate.

Abstract: Embodiments of the present invention are directed to the formation of microprobe tips elements having a variety of configurations. In some embodiments tips are formed from the same building material as the probes themselves, while in other embodiments the tips may be formed from a different material and/or may include a coating material. In some embodiments, the tips are formed before the main portions of the probes and the tips are formed in proximity to or in contact with a temporary substrate.

Abstract: Multilayer probe structures for testing semiconductor die are electrochemically fabricated via depositions of one or more materials in a plurality of overlaying and adhered layers. In some embodiments the structures may include generally helical shaped configurations, helical shape configurations with narrowing radius as the probe extends outward from a substrate, bellows-like configurations, and the like. In some embodiments arrays of multiple probes are provided.

Abstract: Embodiments of the present invention are directed to the formation of microprobe tips elements having a variety of configurations. In some embodiments tips are formed from the same building material as the probes themselves, while in other embodiments the tips may be formed from a different material and/or may include a coating material. In some embodiments, the tips are formed before the main portions of the probes and the tips are formed in proximity to or in contact with a temporary substrate.

Abstract: An integrated circuit is described which include a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface, or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Abstract: Embodiments of the invention provide electrochemical fabrication processes that may be used for the fabrication of space transformers or the co-fabrication of microprobe arrays along with one or more space transformers.

Abstract: Embodiments of the present invention are directed to the formation of microprobe tips elements having a variety of configurations. In some embodiments tips are formed from the same building material as the probes themselves, while in other embodiments the tips may be formed from a different material and/or may include a coating material. In some embodiments, the tips are formed before the main portions of the probes and the tips are formed in proximity to or in contact with a temporary substrate.

Abstract: Embodiments of the invention provide a package for holding an integrated circuit or other electronic component and/or a packaged integrated circuit or electronic component which is formed at least in part via an electrochemical fabrication process from a plurality of adhered layers of conductive and dielectric materials.

Abstract: Pin probes and pin probe arrays are provided that allow electric contact to be made with selected electronic circuit components. Some embodiments include one or more compliant pin elements located within a sheath. Some embodiments include pin probes that include locking or latching elements that may be used to fix pin portions of probes into sheaths. Some embodiments provide for fabrication of probes using multi-layer electrochemical fabrication methods.