Abstract: A method for forming interlevel dielectric layers in multilevel interconnect structures using air as the constituent low-k dielectric material that is compatible with damascene processes without introducing additional process steps. The conductive features characteristic of the damascene process are formed by standard lithographic and etch processes in the mandrel material for each level of the interconnect structure. The conductive features in each level are surrounded by the mandrel material. After all levels of the interconnect structure are formed, a passageway is provided to the mandrel material. An isotropic etchant is introduced through the passageway that selectively etches and removes the mandrel material. The spaces formerly occupied by the mandrel material in the levels of the interconnect structure are filled by air, which operates as a low-k dielectric material.

Abstract: A dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a metallic storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. Preferably, the trench has an aspect ratio of greater than 50. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness.

Abstract: A semi-conductor device includes a silicon substrate. A gate oxide dielectric layer is on the silicon substrate. A gate conductor includes a relatively thin layer of germanium on the dielectric layer. A relatively thick layer of gate conductor material is provided on the layer of germanium. Incorporating germanium at the gate conductor interface with the gate oxide stabilizes the gate oxide by providing a means of drawing charge trapping sites away from the oxide.

Abstract: A semi-conductor device includes a silicon substrate. A gate oxide dielectric layer is on the silicon substrate. A gate conductor includes a relatively thin layer of germanium on the dielectric layer. A relatively thick layer of gate conductor material is provided on the layer of germanium. Incorporating germanium at the gate conductor interface with the gate oxide stabilizes the gate oxide by providing a means of drawing charge trapping sites away from the oxide.

Abstract: A memory cell which comprises a substrate having a top surface; a capacitor extending vertically into the substrate for storing a voltage representing a datum, said capacitor occupying a geometrically shaped horizontal area; a transistor formed above the capacitor and occupying a horizontal area substantially equal to the geometrically shaped horizontal area, and having a vertical device depth, for establishing an electrical connection with the capacitor, in response to a control signal, for reading from, and writing to, the capacitor, wherein the transistor includes a gate formed near the periphery of said horizontal device area and having a vertical depth approximately equal to the vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the body near the top and bottom surfaces and a met

Abstract: A memory cell which comprises a substrate having a top surface; a capacitor extending vertically into the substrate for storing a voltage representing a datum, said capacitor occupying a geometrically shaped horizontal area; a transistor formed above the capacitor and occupying a horizontal area substantially equal to the geometrically shaped horizontal area, and having a vertical device depth, for establishing an electrical connection with the capacitor, in response to a control signal, for reading from, and writing to, the capacitor, wherein the transistor includes a gate formed near the periphery of said horizontal device area and having a vertical depth approximately equal to the vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the body near the top and bottom surfaces and a met

Abstract: A memory cell which comprises a substrate having a top surface; a capacitor extending vertically into the substrate for storing a voltage representing a datum, said capacitor occupying a geometrically shaped horizontal area; a transistor formed above the capacitor and occupying a horizontal area substantially equal to the geometrically shaped horizontal area, and having a vertical device depth, for establishing an electrical connection with the capacitor, in response to a control signal, for reading from, and writing to, the capacitor, wherein the transistor includes a gate formed near the periphery of said horizontal device area and having a vertical depth approximately equal to the vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the body near the top and bottom surfaces and a met

Abstract: A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.

Abstract: A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.

Abstract: A rechargeable electrochemical storage cell comprising a housing, in the interior of which is an anode and a cathode spaced from each other and both provided with a core of glassy carbon, graphite or carbon cloth and both anode and cathode having thereon an electrodeposited coating of poly(2,6-naphthoquinone), said anode and cathode having therebetween an electrolyte of a buffer at a pH in the range of about 6 to 9.

Abstract: Polymers, the surfaces of which have been modified, are disclosed. The polymer surface is modified by embedding therein a second polymer. The modified polymer substantially retains its bulk properties while also possessing, at its surface, properties of the second polymer.

Abstract: Polymer surfaces which are rendered nonthrombogenic are disclosed. Polymers, including hydrophobic polymers, which can be swollen by selected solvents, are rendered nonthrombogenic by absorbing into the surface of said polymers pendant aliphatic side chains which are attached to a linear polymer having reactive pendant groups which are negatively charged or which may be reacted with compounds having a negative charge, such as heparin. The compounds absorbed into the substrate surface have multi-point attachment to the surface.