Patents by Inventor Vaddagiri Srivatsa
Vaddagiri Srivatsa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8661417Abstract: A method of debugging a function upon function exit includes pausing program execution at the time of initializing the function, wherein the function initialization includes saving a set of registers on the stack, recording the value of the stack pointer, configuring a watchpoint register based on the recorded value, wherein the watchpoint register is configured to trap memory references of the function based on the recorded value of the stack pointer, and executing the function. Program execution will pause when it is exiting the function because of stack references made by the function epilogue to restore registers saved on the stack and the configured watchpoint registers.Type: GrantFiled: March 26, 2009Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Prasanna S. Panchamukhi, Vaddagiri Srivatsa
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Patent number: 8522251Abstract: Task placement is influenced within a multiple processor computer. Tasks are classified as either memory bound or CPU bound by observing certain performance counters over the task execution. During a first pass of task load balance, tasks are balanced across various CPUs to achieve a fairness goal, where tasks are allocated CPU resources in accordance to their established fairness priority value. During a second pass of task load balance, tasks are rebalanced across CPUs to reduce CPU resource contention, such that the rebalance of tasks in the second pass does not violate fairness goals established in the first pass. In one embodiment, the second pass could involve re-balancing memory bound tasks across different cache domains, where CPUs in a cache domain share a same last mile CPU cache such as an L3 cache.Type: GrantFiled: January 10, 2011Date of Patent: August 27, 2013Assignee: International Business Machines CorporationInventors: Bharata B. Rao, Vaidyanathan Srinivasan, Vaddagiri Srivatsa
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Patent number: 8352946Abstract: The present disclosure is directed to a method for managing tasks in a computer system having a plurality of CPUs. Each task in the computer system may be configured to indicate a migration ready indicator of the task. The migration ready indicator for a task may be given when the set of live data for that task reduces or its working set of memory changes. The method may comprise associating a migration readiness queue with each of the plurality of CPUs, the migration readiness queue having a front-end and a back-end; analyzing a task currently executing on a particular CPU, wherein the particular CPU is one of the plurality of CPUs; placing the task in the migration readiness queue of the particular CPU based on status of the task and/or the migration ready indicator of the task; and selecting at least one queued task from the front-end of the migration readiness queue of the particular CPU for migration when the particular CPU receives a task migration command.Type: GrantFiled: August 11, 2009Date of Patent: January 8, 2013Assignee: International Business Machines CorporationInventors: Vaddagiri Srivatsa, Manish Gupta
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Publication number: 20120180061Abstract: Task placement is influenced within a multiple processor computer. Tasks are classified as either memory bound or CPU bound by observing certain performance counters over the task execution. During a first pass of task load balance, tasks are balanced across various CPUs to achieve a fairness goal, where tasks are allocated CPU resources in accordance to their established fairness priority value. During a second pass of task load balance, tasks are rebalanced across CPUs to reduce CPU resource contention, such that the rebalance of tasks in the second pass does not violate fairness goals established in the first pass. In one embodiment, the second pass could involve re-balancing memory bound tasks across different cache domains, where CPUs in a cache domain share a same last mile CPU cache such as an L3 cache.Type: ApplicationFiled: January 10, 2011Publication date: July 12, 2012Applicant: International Business Machines CorporationInventors: Bharata B. Rao, Vaidyanathan Srinivasan, Vaddagiri Srivatsa
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Patent number: 8117621Abstract: A method and system for scheduling tasks on a processor, the tasks being scheduled by an operating system to run on the processor in a predetermined order, the method comprising identifying and creating task groups of all related tasks; assigning the tasks in the task groups into a single common run-queue; selecting a task at the start of the run-queue; determining if the task at the start of the run-queue is eligible to be run based on a pre-defined timeslice allocated and on the presence of older starving tasks on the runqueue; executing the task in the pre-defined time slice; associating a starving status to all unexecuted tasks and running all until all tasks in the run-queue complete execution and the run-queue become empty.Type: GrantFiled: October 24, 2007Date of Patent: February 14, 2012Assignee: International Business Machines CorporationInventors: Balbir Singh, Vaddagiri Srivatsa
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Patent number: 7934062Abstract: An improved reader-writer locking for synchronizing access to shared data. When writing the shared data, a writer flag is set and a lock is acquired on the shared data. The shared data may be accessed following the expiration of a grace period and a determination that there are no data readers accessing the shared data. When reading the shared data, the writer flag is tested that indicates whether a data writer is attempting to access the shared data. If the writer flag is not set, the shared data is accessed using a relatively fast read mechanism. If the writer flag is set, the shared data is accessed using a relatively slow read mechanism.Type: GrantFiled: June 22, 2007Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Paul E. McKenney, Vaddagiri Srivatsa, Gautham R. Shenoy
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Publication number: 20110041131Abstract: The present disclosure is directed to a method for managing tasks in a computer system having a plurality of CPUs. Each task in the computer system may be configured to indicate a migration ready indicator of the task. The migration ready indicator for a task may be given when the set of live data for that task reduces or its working set of memory changes. The method may comprise associating a migration readiness queue with each of the plurality of CPUs, the migration readiness queue having a front-end and a back-end; analyzing a task currently executing on a particular CPU, wherein the particular CPU is one of the plurality of CPUs; placing the task in the migration readiness queue of the particular CPU based on status of the task and/or the migration ready indicator of the task; and selecting at least one queued task from the front-end of the migration readiness queue of the particular CPU for migration when the particular CPU receives a task migration command.Type: ApplicationFiled: August 11, 2009Publication date: February 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vaddagiri Srivatsa, Manish Gupta
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Publication number: 20100251026Abstract: A method of debugging a function upon function exit includes pausing program execution at the time of initializing the function, wherein the function initialization includes saving a set of registers on the stack, recording the value of the stack pointer, configuring a watchpoint register based on the recorded value, wherein the watchpoint register is configured to trap memory references of the function based on the recorded value of the stack pointer, and executing the function. Program execution will pause when it is exiting the function because of stack references made by the function epilogue to restore registers saved on the stack and the configured watchpoint registers.Type: ApplicationFiled: March 26, 2009Publication date: September 30, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Prasanna S. Panchamukhi, Vaddagiri Srivatsa
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Publication number: 20090113432Abstract: A method and system for scheduling tasks on a processor, the tasks being scheduled by an operating system to run on the processor in a predetermined order, the method comprising identifying and creating task groups of all related tasks; assigning the tasks in the task groups into a single common run-queue; selecting a task at the start of the run-queue; determining if the task at the start of the run-queue is eligible to be run based on a pre-defined timeslice allocated and on the presence of older starving tasks on the runqueue; executing the task in the pre-defined time slice; associating a starving status to all unexecuted tasks and running all until all tasks in the run-queue complete execution and the run-queue become empty.Type: ApplicationFiled: October 24, 2007Publication date: April 30, 2009Inventors: Balbir Singh, Vaddagiri Srivatsa
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Publication number: 20080320262Abstract: An improved reader-writer locking for synchronizing access to shared data. When writing the shared data, a writer flag is set and a lock is acquired on the shared data. The shared data may be accessed following the expiration of a grace period and a determination that there are no data readers accessing the shared data. When reading the shared data, the writer flag is tested that indicates whether a data writer is attempting to access the shared data. If the writer flag is not set, the shared data is accessed using a relatively fast read mechanism. If the writer flag is set, the shared data is accessed using a relatively slow read mechanism.Type: ApplicationFiled: June 22, 2007Publication date: December 25, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul E. McKenney, Vaddagiri Srivatsa, Gautham R. Shenoy