Patents by Inventor Vadim A. Kushner
Vadim A. Kushner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973112Abstract: A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.Type: GrantFiled: November 29, 2022Date of Patent: April 30, 2024Assignee: Silanna Asia Pte LtdInventors: Vadim Kushner, Nima Beikae
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Publication number: 20230124961Abstract: A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.Type: ApplicationFiled: November 29, 2022Publication date: April 20, 2023Applicant: Silanna Asia Pte LtdInventors: Vadim Kushner, Nima Beikae
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Patent number: 11552168Abstract: A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.Type: GrantFiled: October 16, 2020Date of Patent: January 10, 2023Assignee: Silanna Asia Pte LtdInventors: Vadim Kushner, Nima Beikae
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Publication number: 20220231152Abstract: A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.Type: ApplicationFiled: April 7, 2022Publication date: July 21, 2022Applicant: Silanna Asia Pte LtdInventors: Vadim Kushner, Nima Beikae
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Patent number: 11316037Abstract: A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.Type: GrantFiled: June 5, 2020Date of Patent: April 26, 2022Assignee: Silanna Asia Pte LtdInventors: Vadim Kushner, Nima Beikae
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Publication number: 20210043729Abstract: A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.Type: ApplicationFiled: October 16, 2020Publication date: February 11, 2021Applicant: Silanna Asia Pte LtdInventors: Vadim Kushner, Nima Beikae
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Patent number: 10811497Abstract: A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.Type: GrantFiled: April 17, 2018Date of Patent: October 20, 2020Assignee: Silanna Asia Pte LtdInventors: Vadim Kushner, Nima Beikae
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Publication number: 20200303529Abstract: A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.Type: ApplicationFiled: June 5, 2020Publication date: September 24, 2020Applicant: Silanna Asia Pte LtdInventors: Vadim Kushner, Nima Beikae
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Patent number: 10700187Abstract: A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.Type: GrantFiled: May 30, 2018Date of Patent: June 30, 2020Assignee: Silanna Asia Pte LtdInventors: Vadim Kushner, Nima Beikae
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Publication number: 20190371924Abstract: A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.Type: ApplicationFiled: May 30, 2018Publication date: December 5, 2019Inventors: Vadim Kushner, Nima Beikae
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Publication number: 20190319097Abstract: A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.Type: ApplicationFiled: April 17, 2018Publication date: October 17, 2019Applicant: Silanna Asia Pte LtdInventors: Vadim Kushner, Nima Beikae
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Publication number: 20190312139Abstract: A semiconductor device includes an active region formed over a substrate. The active region includes a FET and a diode. The FET includes one or more FET fingers. Each FET finger includes a FET source region, a FET drain region, and a lateral FET gate electrode. The diode includes one or more diode fingers. Each of the diode fingers includes a diode anode region electrically coupled to the FET source region, a diode cathode region electrically coupled to the FET drain region, and a lateral diode gate electrode electrically coupled to the diode anode region and electrically isolated from the lateral FET gate electrode. The FET fingers are active fingers of the semiconductor device and the diode fingers are dummy fingers of the semiconductor device. The diode is configured to clamp a maximum voltage developed across the FET drain region and the FET source region.Type: ApplicationFiled: April 4, 2018Publication date: October 10, 2019Applicant: Silanna Asia Pte LtdInventors: Shanghui Larry Tu, Vadim Kushner, Eric Vann
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Patent number: 10424661Abstract: A semiconductor device includes an active region formed over a substrate. The active region includes a FET and a diode. The FET includes one or more FET fingers. Each FET finger includes a FET source region, a FET drain region, and a lateral FET gate electrode. The diode includes one or more diode fingers. Each of the diode fingers includes a diode anode region electrically coupled to the FET source region, a diode cathode region electrically coupled to the FET drain region, and a lateral diode gate electrode electrically coupled to the diode anode region and electrically isolated from the lateral FET gate electrode. The FET fingers are active fingers of the semiconductor device and the diode fingers are dummy fingers of the semiconductor device. The diode is configured to clamp a maximum voltage developed across the FET drain region and the FET source region.Type: GrantFiled: April 4, 2018Date of Patent: September 24, 2019Assignee: Silanna Asia Pte LtdInventors: Shanghui Larry Tu, Vadim Kushner, Eric Vann
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Patent number: 9509136Abstract: Systems, methods, and apparatus for ESD protection with adjustable trigger voltage decoupled from DC breakdown voltage for semiconductor devices including field effect transistors (FETs), and particularly to metal-oxide-semiconductors (MOSFETs) fabricated on silicon-on-insulator (“SOI”) and silicon-on-sapphire (“SOS”) substrates are described. The apparatus and method are configured to change reverse biased drain junctions which in turn can control the DC breakdown voltage and the trigger voltage.Type: GrantFiled: March 9, 2015Date of Patent: November 29, 2016Assignee: Peregrine Semiconductor CorporationInventors: Vadim Kushner, Erica Poole
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Publication number: 20160268800Abstract: Systems, methods, and apparatus for ESD protection with adjustable trigger voltage decoupled from DC breakdown voltage for semiconductor devices including field effect transistors (FETs), and particularly to metal-oxide-semiconductors (MOSFETs) fabricated on silicon-on-insulator (“SOI”) and silicon-on-sapphire (“SOS”) substrates are described. The apparatus and method are configured to change reverse biased drain junctions which in turn can control the DC breakdown voltage and the trigger voltage.Type: ApplicationFiled: March 9, 2015Publication date: September 15, 2016Inventors: Vadim Kushner, Erica Poole
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Patent number: 8982516Abstract: An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.Type: GrantFiled: January 25, 2013Date of Patent: March 17, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Amaury Gendron, Chai Ean Gill, Vadim A. Kushner, Rouying Zhan
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Publication number: 20140211346Abstract: An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.Type: ApplicationFiled: January 25, 2013Publication date: July 31, 2014Inventors: Amaury Gendron, Chai Ean Gill, Vadim A. Kushner, Rouying Zhan
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Patent number: 8390092Abstract: An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.Type: GrantFiled: November 12, 2010Date of Patent: March 5, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Amaury Gendron, Chai Ean Gill, Vadim A. Kushner, Rouying Zhan
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Publication number: 20120119331Abstract: An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Inventors: Amaury Gendron, Chai Ean Gill, Vadim A. Kushner, Rouying Zhan
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Publication number: 20100301389Abstract: An electrostatic discharge protection structure includes a first vertical bipolar junction transistor; a second vertical bipolar junction transistor, wherein the second vertical bipolar junction transistor has a common collector with the first vertical bipolar junction transistor, and the common collector has a first conductivity; a horizontal bipolar junction transistor wherein the collector of the horizontal bipolar junction transistor has a second conductivity that is a different conductivity than the first conductivity, and the base of the horizontal bipolar junction transistor is electrically coupled to the common collector of the first vertical bipolar junction transistor and the second vertical bipolar junction transistor; a first avalanche diode electrically coupled to the base and the collector of the first vertical bipolar junction transistor; and a second avalanche diode electrically coupled to the base and the collector of the second vertical bipolar junction transistor.Type: ApplicationFiled: May 29, 2009Publication date: December 2, 2010Inventors: Vadim A. Kushner, Amaury Gendron, Chai Ean E. Gill