Abstract: A second order filter-delay element for use in a generalized analog transversal equalizer is described which provides phase and group delay responses equivalent to low-pass filters of third and fourth order. In addition, the filter-delay element provides sufficient values of delays required for proper operations of the analog generalized transversal equalizer despite having a low order. In addition, a method of generating the lower order filter-delay element is described. Also, a circuit embodying an active C-transconductor realization of a second order filter-delay element for use in a generalized analog transversal equalizer with a transfer function designed as a result of performing the method is described.

Abstract: A magnetic recording readback channel having an equalizer and a self synchronizer is described. The equalizer equalizing an input signal to an approximation of selected waveform. The equalizer including an analog, continuous-time frequency-domain prefilter which generates a preconditioned signal from the input signal. The equalizer further including a sampler which derives discrete-time samples appropriate for sequential sampled data decoding from the preconditioned signal and a sampling clock. The self-synchronizer generating the sampling clock from differentiation of a readback signal by utilizing an analog continuous-time filtering channel which is different from the equalizer and configured in parallel to the equalizer. The self-synchronizer including a phase locked loop which generates the sampling clock from detected magnetic transitions on a magnetic medium and which corrects the sampling clock based upon moments of detected peak pulses in the readback signal.

Abstract: Improved self-synchronization in a sampled magnetic recording channel employing time-domain equalization. The channel includes a time-domain equalizer which filters an input, readback signal to an approximation of a selected target waveform. The equalizer includes a plurality of serially connected analog filter sections having associated tap locations, analog multipliers which multiply the tap signals present at the tap locations by tap weight signals to generate product signals and a summer which sums the product signals to generate an equalized output signal. A self-synchronization circuit, responsive to the main tap of the equalizer, synchronizes the data recovery process used by the channel with the rate of the readback signals provided to the channel.

Abstract: An analog, adaptive generalized transversal equalizer for use in the filtering system of a disc drive PRML read channel, the transversal equalizer employing the use of non-ideal delay elements. The filtering system comprises the equalizer connected in series with an adaptive, analog prefilter. The prefilter is comprised of a plurality of serially connected, adaptive, analog filter stages having variable transfer functions determined by adaptive parameter signals received by the filter stages. The generalized transversal equalizer comprises a plurality of serially connected, adaptive, analog low pass filters, having taps on either side of each low pass filter, a plurality of multipliers that receive signals at the tap locations of the delay circuit, and a summing circuit that receives the outputs of the multipliers.

Abstract: A disc drive system includes a plurality of subsystems. At least one of the subsystems includes a filter which is completely integrated using a synthetic integrated circuit element.

Abstract: An adaptive, analog filter system of a PRML [PARTIAL RESPONSE MAXIMUM LIKELIHOOD ] read channel of a disc drive comprising an adaptive, analog transversal equator connected in series with an adaptive, analog prefilter. The prefilter is comprised of a plurality of serially connected, adaptive, analog filter stages having variable transfer functions determined by adaptive parameter signals received by the filter stages. The transversal equalizer is comprised of a delay circuit, comprised of a plurality of serially connected, adaptive, analog sixth order low pass filters, that is tapped to either side of each low pass filter, a plurality of analog multipliers that receive signals at the tap locations of the delay circuit, and a summing circuit that receives the outputs of the multipliers.

Abstract: Method and apparatus for controlling the timing of the sampling of signals and signal amplitude in a PRML read channel. A VCO generates a read clock and a clock generator connected to the VCO generates even and odd clock signals corresponding to even and odd cycles of operation of the VCO. Serially connected even sample and hold circuits respond to clock signals to store samples of the read channel signal taken during successive odd cycles and serially connected odd sample and hold circuits store samples taken during successive even cycles. Comparator circuits compare the samples taken in each cycle to reference signals and the comparisons are clocked through two stage, even and odd shift registers to provide estimates of the presence or absence of nonzero samples for each even and odd cycle.

Abstract: A maximum likelihood detector for a disc drive in which data files are stored along tracks as a sequence of magnetically written data elements that give rise to a signal in the disc drive read chapel. The detector includes even and odd Viterbi decoders that determine the most likely even and odd subsequences of data elements from even and odd samples of the signal and a postcoder that generates the most likely sequence of bits of encoded user data from the subsequences.

Abstract: A disc drive system includes a plurality of subsystems. At least one of the subsystems includes a filter which is completely integrated using a synthetic integrated circuit element.

Abstract: Methods and apparatus are disclosed which utilize isotropic/perpendicular medium for performing high density digital magnetic recording. According to the preferred embodiment of the invention, the l's of a binary code are deeply imprinted on the medium by switching off the current in the winding of a magnetic ring head. The l's so imprinted on the medium are each represented by a copy of a part of the fringing field of the ring head. Each imprinted field has the appearance of a "horseshoe" pattern of magnetization. During readback these imprinted patterns correlate extremely well with the sensitivity function (the fringing field) of the ring head/readback transducer. The invention utilizes this inherently present correlation, together with a combination of longitudinal and vertical recording techniques, to provide methods and apparatus well suited to locate signals buried in noise and yield improved overall readback performance in a high density environment.

Abstract: A phase lock loop includes a phase shift apparatus to provide a plurality (i.e., four) phase-shifted clock signals from the VCO. A phase selector is responsive to a triggering signal from a one-shot multivibrator to select the one phase-shifted clock signal next following termination of the trigger signal. The one-shot is responsive to a change between the read and write mode to initiate operation of the phase selector. As a result, the initial phase error between the input signal (read pulses or write clock) and the clock signal of the phase lock loop is no more than 1/8 window.

Abstract: A 1,7 decoder is repeatedly initialized during reading of the synchrofield of the record. The decoder includes an oscillator responsive to the record to produce a binary read signal having a frequency f. A first divider produces a source data clock signal having a frequency 2/3 f. A second divider produces a data partition clock signal having a frequency 1/3 f. A phase synchronizer is responsive to the data partition clock signal to synchronize the source data clock signal. An initializer is responsive to the read signal recovered from the preamble of the record to synchronize the data partition clock signal.

Abstract: A 3/2 frequency divider employs two D-type flip-flops, an OR gate and an AND gate arranged to respond to an input signal at a frequency f to derive an output signal at a frequency 2/3 f. The frequency divider is employed in a code converter to encode or decode 1, 7, 2, 3 codes.

Abstract: An encoding/decoding system for 1,7,2,3 codes employs an oscillator having a frequency f and dividers providing signals at frequencies equal to 1/3 f and 2/3 f. A code converter is responsive to the three signals to encode or decode data. A 3/2 frequency divider employs two D-type flip-flops, an OR gate and an AND gate arranged to respond to an input signal at a frequency f to derive an output signal at a frequency 2/3 f.

Abstract: Run length limited codes, such as (1,7) codes are recovered with a dual channel recovery system in which the high resolution channel normally supplies the output (recovered) signal. The low resolution channel includes a detector, such as a delay device and gate, to detect a predetermined absence of transitions in the low resolution signal (which is indicative of long strings of successive zeros) to inhibit the high resolution channel from supplying the output. The result is to effectively block the high resolution channel from providing a false output.

Abstract: A retriggerable monostable multivibrator according to the present invention comprises a bistable device, such as S-R latch, responsive to the output of a pulse former to provide a set output. A propagation chain, comprising a plurality of serially arranged gates, propagates the latch output to form a delayed reset signal. The reset signal operates to reset the bistable latch. Gate means is connected to the true output of the latch, and to the propagation chain, to provide an output pulse for the duration of the true output and reset signal. The gates of the propagation chain are also connected to the pulse former so that the propagation of the reset signal is terminated in the event a second input pulse occurs prior to termination of the reset signal.

Abstract: A dual channel readback recovery circuit includes a high resolution channel and a low resolution channel and a data latch. A logical filter in one or both channels rejects signals that are followed by other signals if they are spaced apart less than the rejection time interval allowed by the code used. Polarity qualifying logic rejects signals in the channel that are not matched in polarity.

Abstract: A phase comparator generates a reference pulse equal in duration to one bit cell, and a variable pulse having a duration representative of the duration and time displacement of the leading edge of a data pulse from the center of the bit cell. The phase comparator includes two D-type flip-flops arranged so that the variable pulse is initiated by the leading edge of the data pulse in the one bit cell, the reference pulse is initiated by the edge of the clock pulse at the end of the one bit cell, and both pulses are terminated by the edge of the clock pulse at the end of the next bit cell. Hence, only clock edges at the bounds of the bit cell affect the pulse durations and the apparatus is insensitive to clock asymmetry.

Abstract: A decoder for the 2,7 variable length code. A four-bit shift register sliding block decoder detects the presence of the code's four-bit ending sequence and provides decoded binary output. The decoder has only a three-bit binary error propagation.

Abstract: A dual channel read recovery system having a high resolution channel and a low resolution channel and logic for recovering digital information from the high and low resolution signals from the channels, is improved by the inclusion of a variable delay in the low resolution channel. The variable delay is responsive to the high and low resolution signals to more closely match the delays in both channels.