Abstract: A frequency synthesizer includes: a frequency source generating a reference signal that includes a plurality of pulses having periodicity based on a reference frequency; a feedback loop that includes, a phase detector circuit, a loop filter, a controlled oscillator that generates an output signal at an output, and a loop divide circuit; a non-linear circuit element at an input of the phase detector circuit, which generates intermodulation distortion that causes at least one spurious signal at the output; and a controller controlling the loop divide circuit and the non-linear circuit element. The frequency synthesizer further includes a dither circuit that adjusts the timing of some of the pulses of the reference signal based on a parameter provided by the controller to the non-linear circuit element, thereby, providing a jittered reference signal to the non-linear circuit element for attenuating the at least one spurious signal at the output.

Abstract: A frequency synthesizer includes: a frequency source generating a reference signal that includes a plurality of pulses having periodicity based on a reference frequency; a feedback loop that includes, a phase detector circuit, a loop filter, a controlled oscillator that generates an output signal at an output, and a loop divide circuit; a non-linear circuit element at an input of the phase detector circuit, which generates intermodulation distortion that causes at least one spurious signal at the output; and a controller controlling the loop divide circuit and the non-linear circuit element. The frequency synthesizer further includes a dither circuit that adjusts the timing of some of the pulses of the reference signal based on a parameter provided by the controller to the non-linear circuit element, thereby, providing a jittered reference signal to the non-linear circuit element for attenuating the at least one spurious signal at the output.

Abstract: A system and method for reducing the transient responses in a phase lock loop (PLL) (100) with variable oscillator gain is disclosed. The system includes a charge pump (104) having an adapt mode and a normal mode of operation. The charge pump (104) also includes controlled trickle currents from current sources (208), (210) which are applied to the output (105), (107) of charge pump (104) to minimize the transient responses of the PLL (100). A programmable delay is provided in the charge pump (104) and is configured using a controller (122) based on the variable oscillator gain for the PLL (100). The configured programmable delay is used in the adapt mode of operation for adding a trickle current from the current source (210) to the adapt mode output (107).

Abstract: A system and method for reducing the transient responses in a phase lock loop (PLL) (100) with variable oscillator gain is disclosed. The system includes a charge pump (104) having an adapt mode and a normal mode of operation. The charge pump (104) also includes controlled trickle currents from current sources (208), (210) which are applied to the output (105), (107) of charge pump (104) to minimize the transient responses of the PLL (100). A programmable delay is provided in the charge pump (104) and is configured using a controller (122) based on the variable oscillator gain for the PLL (100). The configured programmable delay is used in the adapt mode of operation for adding a trickle current from the current source (210) to the adapt mode output (107).

Abstract: A system and method for reducing a transient response in a phase lock loop (PLL) (100) is disclosed. The system includes an adapt mode charge pump (204), a normal mode charge pump (206) and the use of controlled trickle currents (208), (210) applied to those charge pumps to minimize a transient response of the PLL (100).

Abstract: A system and method for reducing a transient response in a phase lock loop (PLL) (100) is disclosed. The system includes an adapt mode charge pump (204), a normal mode charge pump (206) and the use of controlled trickle currents (208), (210) applied to those charge pumps to minimize a transient response of the PLL (100).