Abstract: A CDS device of an image sensor having a pixel array includes first comparators, second comparators and third comparators. The first comparators are coupled to columns of the pixel array, and generate a positive amplified signal and a negative amplified signal by comparing the analog signal and a ramp signal. The second comparators are coupled to a first set of the first comparators coupled to first columns of the pixel array, and generate a first comparison signal enabled to a first logic level by comparing the positive amplified signal and the negative amplified signal. The third comparators are coupled to a second set of the first comparators coupled to second columns of the pixel array, and generate a second comparison signal enabled to a second logic level by comparing the positive amplified signal and the negative amplified signal.

Abstract: A CDS device of an image sensor having a pixel array includes first comparators, second comparators and third comparators. The first comparators are coupled to columns of the pixel array, and generate a positive amplified signal and a negative amplified signal by comparing the analog signal and a ramp signal. The second comparators are coupled to a first set of the first comparators coupled to first columns of the pixel array, and generate a first comparison signal enabled to a first logic level by comparing the positive amplified signal and the negative amplified signal. The third comparators are coupled to a second set of the first comparators coupled to second columns of the pixel array, and generate a second comparison signal enabled to a second logic level by comparing the positive amplified signal and the negative amplified signal.

Abstract: In at least one example embodiment, a counter circuit includes a latch stage configured to generate a latch stage output clock based on a first rising edge of an enable signal, a state of a counter clock at a previous falling edge of the enable signal, and a state of the output clock at the previous falling edge of the enable signal such that the latch stage output clock and the counter clock have a different state if the state of the counter clock at the previous falling edge and the state of the output clock at the previous falling edge are the same and such that the latch stage output clock and the counter clock have a same state if the state of the counter clock at the previous falling edge and the state of the output clock at the previous falling edge are different.

Abstract: At least one example embodiment provides for a frequency divider system including a delay unit configured to receive a first input clock signal having a first input clock frequency and a requirement and output a modified clock signal, and a frequency divider configured to receive the modified clock signal and output an output clock signal having an output clock frequency. The output clock frequency is an odd or even integer division of the first input clock frequency based on the requirement such as an input control word.

Abstract: In at least one example embodiment, a counter circuit includes a latch stage configured to generate a latch stage output clock based on a first rising edge of an enable signal, a state of a counter clock at a previous falling edge of the enable signal, and a state of the output clock at the previous falling edge of the enable signal such that the latch stage output clock and the counter clock have a different state if the state of the counter clock at the previous falling edge and the state of the output clock at the previous falling edge are the same and such that the latch stage output clock and the counter clock have a same state if the state of the counter clock at the previous falling edge and the state of the output clock at the previous falling edge are different.

Abstract: An apparatus and method for calibrating a ramp slope value of a ramp signal to increase the accuracy of the slope of the ramp signal used within CMOS image sensors. An image sensor includes an active pixel sensor (APS) array, a ramp signal generator and an analog-to-digital converter (ADC). The APS array is configured to generate a reset signal and an image signal for a pixel of a selected row of the APS array. The ramp signal generator is configured to generate a ramp signal, a ramp slope value of the ramp signal being adjusted based on a slope control signal. The ADC is configured to generate a digital code based on the ramp signal and a difference between the reset signal and the image signal.

Abstract: At least one example embodiment provides for a frequency divider system including a delay unit configured to receive a first input clock signal having a first input clock frequency and a requirement and output a modified clock signal, and a frequency divider configured to receive the modified clock signal and output an output clock signal having an output clock frequency. The output clock frequency is an odd or even integer division of the first input clock frequency based on the requirement such as an input control word.

Abstract: An apparatus and method for calibrating a ramp slope value of a ramp signal to increase the accuracy of the slope of the ramp signal used within CMOS image sensors. An image sensor includes an active pixel sensor (APS) array, a ramp signal generator and an analog-to-digital converter (ADC). The APS array is configured to generate a reset signal and an image signal for a pixel of a selected row of the APS array. The ramp signal generator is configured to generate a ramp signal, a ramp slope value of the ramp signal being adjusted based on a slope control signal. The ADC is configured to generate a digital code based on the ramp signal and a difference between the reset signal and the image signal.

Abstract: Embodiments of the present invention provide for reducing leakage associated with hold capacitors used in the processing of analog outputs from an image sensor. In some embodiments, a circuit configuration provides for load balancing of a hold capacitor associated with the image processor to prevent voltage droop across the storage capacitor. In certain embodiments, double sampling of the image sensor is provided for and two hold capacitors are configured to have balanced loads across each of the capacitor's terminals so as to prevent associated voltage droop. In embodiments of the present invention, a discharge mechanism associated with the hold capacitors is configured to only connect to the hold capacitor during discharge, in order to prevent leakage from the capacitor. In certain embodiments of the present invention, load balancing of the hold capacitors may be achieved by using symmetrical circuit design and circuit layout.