Patents by Inventor Vadim Gouterman

Vadim Gouterman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100169858
    Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 1, 2010
    Inventors: Vaughn Betz, Jordan Swartz, Vadim Gouterman
  • Patent number: 7441208
    Abstract: The process of designing an integrated circuit (“IC”) to implement a generalized circuit design includes a signoff between a front-end part of the process and a back-end part of the process. This signoff preferably takes place after at least some global routing has been done for the IC implementation, but before all final detailed routing is done for that implementation.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: October 21, 2008
    Assignee: Altera Corporation
    Inventors: Ketan Padalia, Vaughn Betz, Vadim Gouterman
  • Patent number: 7412680
    Abstract: A method for designing a system on an integrated circuit includes synthesizing the system. The system is placed on the integrated circuit. Buffer insertion is performed while selecting new branch points during routing of the system.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: August 12, 2008
    Assignee: Altera Corporation
    Inventors: Vadim Gouterman, Vaughn Betz, Mark Bourgeault
  • Patent number: 6915493
    Abstract: One embodiment of the invention provides a system that communicates feedback from a compactor to a router to facilitate layout of an integrated circuit. The system operates by first receiving a routing for a cell in an integrated circuit layout at the compactor. The system then attempts to compact the routing. If compaction of the routing fails, the system identifies an infeasibility path in the routing and rips up traces on the infeasibility path while leaving other traces undisturbed. The system then adjusts parameters associated with the routing process and reroutes the cell using the adjusted parameters. The system then attempts to compact this rerouting.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: July 5, 2005
    Assignee: Synopsys, Inc.
    Inventors: Edward G. Moulding, Vadim Gouterman
  • Publication number: 20040123252
    Abstract: One embodiment of the invention provides a system that communicates feedback from a compactor to a router to facilitate layout of an integrated circuit. The system operates by first receiving a routing for a cell in an integrated circuit layout at the compactor. The system then attempts to compact the routing. If compaction of the routing fails, the system identifies an infeasibility path in the routing and rips up traces on the infeasibility path while leaving other traces undisturbed. The system then adjusts parameters associated with the routing process and reroutes the cell using the adjusted parameters. The system then attempts to compact this rerouting.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Applicant: Numerical Technologies Inc.
    Inventors: Edward G. Moulding, Vadim Gouterman