Patents by Inventor Vadim Gutnik
Vadim Gutnik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10177851Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: GrantFiled: July 12, 2017Date of Patent: January 8, 2019Assignee: INPHI CORPORATIONInventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Paul Voois, Ramiro Rogelio Lopez, Jorge Manuel Finochietto, Norman L. Swenson, Mario Rafael Hueda, Hugo Santiago Carrer, Vadim Gutnik, Adrián Ulises Morales, Martin Ignacio Del Barco, Martin Carlos Asinari, Federico Nicolas Paredes, Alfredo Javier Taddei, Mauro Marcelo Bruni, Damian Alfonso Morero, Facundo Abel Alcides Ramos, María Laura Ferster, Elvio Adrian Serrano, Pablo Gustavo Quiroga, Roman Antonio Arenas, Matias German Schnidrig, Alejandro Javier Schwoykoski
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Patent number: 10038506Abstract: A transceiver for fiber optic communications. The transceiver can include a transmitter module having a transmitter host interface configured to receive an input host signal; a transmitter framer configured to frame the input host signal and to generate a framed host signal; and a transmitter coder configured to encode the framed host signal to generate an encoded host signal for transmission over a communication channel. The transceiver can also include a receiver module having a bulk chromatic dispersion, fiber length estimation, and coarse carrier recovery circuit configured to equalize a digital input ingress signal to generate an equalized ingress signal; a receiver framer configured to frame the equalized ingress signal to generate a framed ingress signal; and a receiver host interface configured to output the framed ingress signal. The receiver host interface is compatible with a framing protocol of the receiver framer.Type: GrantFiled: November 1, 2017Date of Patent: July 31, 2018Assignee: INPHI CORPORATIONInventors: Diego Ernesto Crivelli, Mario Rafael Hueda, Hugo Santiago Carrer, Jeffrey Zachan, Vadim Gutnik, Martin Ignacio Del Barco, Ramiro Rogelio Lopez, Shih Cheng Wang, Geoffrey O. Hatcher, Jorge Manuel Finochietto, Michael Yeo, Andre Chartrand, Norman L. Swenson, Paul Voois, Oscar Ernesto Agazzi
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Publication number: 20180107221Abstract: Described herein is a LIDAR device that may include a transmitter, first and second receivers, and a rotating platform. The transmitter may be configured to emit light having a vertical beam width. The first receiver may be configured to detect light at a first resolution while scanning the environment with a first FOV and the second receiver may be configured to detect light at a second resolution while scanning the environment with a second FOV. In this arrangement, the first resolution may be higher than the second resolution, the first FOV may be at least partially different from the second FOV, and the vertical beam width may encompass at least a vertical extent of the first and second FOVs. Further, the rotating platform may be configured to rotate about an axis such that the transmitter and first and second receivers each move based on the rotation.Type: ApplicationFiled: October 17, 2016Publication date: April 19, 2018Inventors: Pierre-Yves Droz, Caner Onal, William McCann, Bernard Fidric, Vadim Gutnik, Laila Mattos, Rahim Pardhan
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Publication number: 20180062760Abstract: A transceiver for fiber optic communications. The transceiver can include a transmitter module having a transmitter host interface configured to receive an input host signal; a transmitter framer configured to frame the input host signal and to generate a framed host signal; and a transmitter coder configured to encode the framed host signal to generate an encoded host signal for transmission over a communication channel. The transceiver can also include a receiver module having a bulk chromatic dispersion, fiber length estimation, and coarse carrier recovery circuit configured to equalize a digital input ingress signal to generate an equalized ingress signal; a receiver framer configured to frame the equalized ingress signal to generate a framed ingress signal; and a receiver host interface configured to output the framed ingress signal. The receiver host interface is compatible with a framing protocol of the receiver framer.Type: ApplicationFiled: November 1, 2017Publication date: March 1, 2018Inventors: Diego Ernesto CRIVELLI, Mario Rafael HUEDA, Hugo Santiago CARRER, Jeffrey ZACHAN, Vadim GUTNIK, Martin Ignacio DEL BARCO, Ramiro Rogelio LOPEZ, Shih Cheng WANG, Geoffrey O. HATCHER, Jorge Manuel FINOCHIETTO, Michael YEO, Andre CHARTRAND, Norman L. SWENSON, Paul VOOIS, Oscar Ernesto AGAZZI
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Patent number: 9838140Abstract: A transceiver for fiber optic communications.Type: GrantFiled: May 16, 2017Date of Patent: December 5, 2017Assignee: INPHI CORPORATIONInventors: Diego Ernesto Crivelli, Mario Rafael Hueda, Hugo Santiago Carrer, Jeffrey Zachan, Vadim Gutnik, Martin Ignacio del Barco, Ramiro Rogelio Lopez, Shih Cheng Wang, Geoffrey O. Hatcher, Jorge Manuel Finochietto, Michael Yeo, Andre Chartrand, Norman L. Swenson, Paul Voois, Oscar Ernesto Agazzi
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Publication number: 20170317759Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: ApplicationFiled: July 12, 2017Publication date: November 2, 2017Inventors: Oscar Ernesto AGAZZI, Diego Ernesto CRIVELLI, Paul VOOIS, Ramiro Rogelio LOPEZ, Jorge Manuel FINOCHIETTO, Norman L. SWENSON, Mario Rafael HUEDA, Hugo Santiago CARRER, Vadim GUTNIK, Adrián Ulises MORALES, Martin Ignacio DEL BARCO, Martin Carlos ASINARI, Federico Nicolas PAREDES, Alfredo Javier TADDEI, Mauro Marcelo BRUNI, Damian Alfonso MORERO, Facundo Abel Alcides RAMOS, María Laura FERSTER, Elvio Adrian SERRANO, Pablo Gustavo QUIROGA, Roman Antonio ARENAS, Matias German SCHNIDRIG, Alejandro Javier SCHWOYKOSKI
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Patent number: 9735881Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: GrantFiled: May 6, 2016Date of Patent: August 15, 2017Assignee: INPHI CORPORATIONInventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Paul Voois, Ramiro Rogelio Lopez, Jorge Manuel Finochietto, Norman L. Swenson, Mario Rafael Hueda, Hugo Santiago Carrer, Vadim Gutnik, Adrián Ulises Morales, Martin Ignacio del Barco, Martin Carlos Asinari, Federico Nicolas Paredes, Alfredo Javier Taddei, Mauro M. Bruni, Damian Alfonso Morero, Facundo Abel Alcides Ramos, María Laura Ferster, Elvio Adrian Serrano, Pablo Gustavo Quiroga, Roman Antonio Arenas, Matias German Schnidrig, Alejandro Javier Schwoykoski
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Patent number: 9673910Abstract: A transceiver for fiber optic communications.Type: GrantFiled: February 23, 2015Date of Patent: June 6, 2017Assignee: Clariphy Communications, Inc.Inventors: Diego Ernesto Crivelli, Mario Rafael Hueda, Hugo Santiago Carrer, Jeffrey Zachan, Vadim Gutnik, Martin Ignacio del Barco, Shih Cheng Wang, Geoffrey O. Hatcher, Jorge Manuel Finochietto, Michael Yeo, Andre Chartrand, Norman L. Swenson, Paul Voois, Oscar Ernesto Agazzi, Ramiro Rogelio Lopez
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Patent number: 9606573Abstract: Circuitry accepts an input signal and distributes the input signal to a plurality of locations within the circuitry. The circuitry includes a first circuit element and a second circuit element. The circuitry further includes a first plurality of wire segments that are substantially aligned to form a first bundle, and include a first wire segment. The circuitry further includes a second plurality of wire segments that are substantially aligned to form a second bundle, and have a second wire segment. An intersection element of the first bundle and the second bundle includes a first interconnecting wire segment that connects the first wire segment and the second wire segment, and the input signal is routed from the first wire segment to the second wire segment via the first interconnecting wire segment. The input signal is further transmitted to the second element from the second wire segment.Type: GrantFiled: June 26, 2015Date of Patent: March 28, 2017Assignee: Altera CorporationInventors: Carl Ebeling, Dana How, Herman Henry Schmit, Vadim Gutnik, Ramanand Venkata
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Patent number: 9337934Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.Type: GrantFiled: November 29, 2013Date of Patent: May 10, 2016Assignee: ClariPhy Communications, Inc.Inventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Paul Voois, Ramiro Rogelio Lopez, Jorge Manuel Finochietto, Norman L. Swenson, Mario Rafael Hueda, Hugo Santiago Carrer, Vadim Gutnik, Ulises Morales, Martin Ignacio del Barco, Martin Carlos Asinari, Federico Nicolas Paredes, Alfredo Javier Taddei, Mauro M. Bruni, Damian Alfonso Morero, Facundo Abel Alcides Ramos, Laura Maria Ferster, Elvio Adrian Serrano, Pablo Gustavo Quiroga, Roman Antonio Arenas, Matias German Schnidrig, Alejandro Javier Schwoykoski
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Patent number: 9319061Abstract: Apparatus and methods for digital-to-analog conversion are disclosed. In one embodiment, an electronic system includes a bias circuit and a digital-to-analog converter (DAC) including an input that receives a digital input signal and an output that drives a transmission line. The digital input signal can be used to control a magnitude and polarity of an output current of the DAC. The DAC further includes one or more p-type metal oxide semiconductor (PMOS) termination transistors that receive a first bias voltage from the bias circuit and one or more n-type metal oxide semiconductor (NMOS) termination transistors that receive a second bias voltage from the bias circuit. The bias circuit controls the voltage levels of the first and second bias voltages to control the termination transistors' small signal resistance to actively terminate the DAC's output.Type: GrantFiled: December 18, 2014Date of Patent: April 19, 2016Assignee: ClariPhy Communications, Inc.Inventors: Morteza Azarmnia, Vadim Gutnik, William Vanscheik
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Patent number: 9165170Abstract: An RFID tag is configured to adjust its current clock frequency to conserve tag power while receiving a reader signal and/or backscattering a signal. The tag may determine whether to adjust its current clock frequency based on one or more timing parameters, which may be determined from a reader command and/or from a signal to be backscattered. The counting rate and/or limit of a tag counter and/or the power supplied to a tag component may also be adjusted. The current tag clock frequency may be adjusted during the signal reception/backscattering process and optionally restored once the process is completed.Type: GrantFiled: May 11, 2015Date of Patent: October 20, 2015Assignee: Impinj, Inc.Inventors: Vadim Gutnik, Scott A. Cooper, John D. Hyde, Theron Stanford
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Patent number: 9064196Abstract: An RFID tag is configured to adjust its current clock frequency to conserve tag power while receiving a reader signal and/or backscattering a signal. The tag may determine whether to adjust its current clock frequency based on one or more timing parameters, which may be determined from a reader command and/or from a signal to be backscattered. The counting rate and/or limit of a tag counter and/or the power supplied to a tag component may also be adjusted. The current tag clock frequency may be adjusted during the signal reception/backscattering process and optionally restored once the process is completed.Type: GrantFiled: May 2, 2012Date of Patent: June 23, 2015Assignee: Impinj, Inc.Inventors: Vadim Gutnik, Scott A. Cooper, John D. Hyde, Theron Stanford
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Patent number: 8947281Abstract: Apparatus and methods for digital-to-analog conversion are disclosed. In one embodiment, an electronic system includes a bias circuit and a digital-to-analog converter (DAC) including an input that receives a digital input signal and an output that drives a transmission line. The digital input signal can be used to control a magnitude and polarity of an output current of the DAC. The DAC further includes one or more p-type metal oxide semiconductor (PMOS) termination transistors that receive a first bias voltage from the bias circuit and one or more n-type metal oxide semiconductor (NMOS) termination transistors that receive a second bias voltage from the bias circuit. The bias circuit controls the voltage levels of the first and second bias voltages to control the termination transistors' small signal resistance to actively terminate the DAC's output.Type: GrantFiled: March 13, 2014Date of Patent: February 3, 2015Assignee: ClariPhy Communications, Inc.Inventors: Morteza Azarmnia, Vadim Gutnik, William Vanscheik
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Patent number: 8224610Abstract: A method of calibrating an oscillator within a Radio-Frequency Identification (RFID) tag includes storing a plurality of calibration values within a memory structure. Each of the calibration values corresponds to a respective oscillation frequency of the oscillator. A selected calibration value is selected from the plurality of calibration values stored, according to a first selection criterion. The oscillator is then calibrated in accordance with the selected calibration value.Type: GrantFiled: July 26, 2006Date of Patent: July 17, 2012Assignee: Impinj, Inc.Inventors: Christopher J. Diorio, Vadim Gutnik, Todd E. Humes
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Patent number: 8193912Abstract: RFID tags are configured to adjust their clock frequency in order to meet predefined limits for reply frequencies to conserve tag power. A deviation of computed tag reply frequency from a reader commanded reply frequency is used to determine an adjustment to the tag clock frequency. The tag clock frequency may be adjusted during backscatter and restored once backscattering is completed.Type: GrantFiled: March 12, 2009Date of Patent: June 5, 2012Assignee: Impinj, Inc.Inventors: Vadim Gutnik, Scott A. Cooper, John D. Hyde
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Patent number: 7808823Abstract: Two floating gate devices are arranged in a redundant configuration in a non-volatile memory (NVM) of a Radio Frequency Identification (RFID) tag such that stress induced leakage current (SILC) or other failures do not result in a complete loss of memory storage. The redundant NVM may be arranged as a series configuration, a parallel configuration, a single-ended device, a differential device, a simple logic circuit function, and/or a complex logic circuit function.Type: GrantFiled: January 26, 2008Date of Patent: October 5, 2010Assignee: Virage Logic CorporationInventors: Yanjun Ma, William T. Colleran, Vadim Gutnik
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RFID tags circuits and methods for sensing own power to predetermine feasibility of requested action
Patent number: 7733227Abstract: Feasibility of a requested action by a reader is predetermined in an RFID tag based on an available tag power level. A pretest that is designed to consume artificially high levels of power is performed and the power level monitored to determine if a preset condition is met. The pretest may include activation of selected components such as a memory and associated support circuitry. If the preset condition is not met, the requested action is aborted and an error message transmitted to the reader.Type: GrantFiled: January 17, 2007Date of Patent: June 8, 2010Assignee: Impinj, Inc.Inventors: Alberto Pesavento, Vadim Gutnik, John D. Hyde -
Patent number: 7679957Abstract: Two floating gate devices are arranged in a redundant configuration in a non-volatile memory (NVM) such that stress induced leakage current (SILC) or other failures do not result in a complete loss of memory storage. The redundant NVM may be arranged as a series configuration, a parallel configuration, a single-ended device, a differential device, a simple logic circuit function, a complex logic circuit function, and/or as part of an RFID tag system.Type: GrantFiled: April 15, 2005Date of Patent: March 16, 2010Assignee: Virage Logic CorporationInventors: Yanjun Ma, William T. Colleran, Vadim Gutnik
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Patent number: 7571359Abstract: Multiple clock circuits are connected by phase detector circuits to generate and synchronize local clock signals. For example, a clock distribution circuit includes a first clock circuit that is configured to generate a first clock signal in response to a first error signal, and a second clock circuit that is configured to generate a second clock signal in response to the first error signal. A first phase detector circuit connects the first clock circuit to the second clock circuit and is configured to generate the first error signal in response to the first and the second clock signals.Type: GrantFiled: July 31, 2001Date of Patent: August 4, 2009Assignee: Massachusetts Institute of TechnologyInventors: Vadim Gutnik, Anantha Chandrakasan