Patents by Inventor Vadim Heyfitch

Vadim Heyfitch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11127643
    Abstract: A device includes a die with perimeters associated therewith, a substrate, and a test channel. The die is coupled to the substrate via a plurality of C4 bumps on a first side of the substrate. The substrate has connections on a second side of the substrate, opposite to the first side. A first connection connects a C4 bump on the first side of the substrate to a connection on the second side using a metal layer. The test channel is positioned within the substrate and further positioned outside of the perimeter of the die coupled to the substrate. The test channel is positioned at substantially a same depth as the metal layer of the first connection. A probe connecting to the test channel via pads positioned on a same side of the substrate that provides electrical characteristics that is substantially the same as electrical characteristics of the first connection.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: September 21, 2021
    Assignee: XILINX, INC.
    Inventors: Vadim Heyfitch, Jaspreet Singh Gandhi
  • Publication number: 20190259695
    Abstract: A chip package and method of fabricating the same are described herein. The chip package includes a high speed data transmission line that has an inter-die region through which a signal transmission line couples a first die to a second die. The signal transmission line has a resistance greater than an equivalent base resistance (EBR) of a copper line, which reduces oscillation within the transmission line.
    Type: Application
    Filed: February 22, 2018
    Publication date: August 22, 2019
    Applicant: Xilinx, Inc.
    Inventors: Jaspreet Singh Gandhi, Vadim Heyfitch
  • Patent number: 9066391
    Abstract: A passive peaking circuit is formed in part from a passive step-down impedance transformer that interconnects the light source driver to the light source. The step-down impedance transformer has impedance that decreases in a continuous or discrete manner in the direction from the light source driver circuit to the light source. The passive peaking circuit peaks the electrical drive signal being delivered from the light source driver circuit to the light source, thereby widening the eye opening.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: June 23, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Vadim Heyfitch
  • Publication number: 20150156832
    Abstract: A passive peaking circuit is formed in part from a passive step-down impedance transformer that interconnects the light source driver to the light source. The step-down impedance transformer has impedance that decreases in a continuous or discrete manner in the direction from the light source driver circuit to the light source. The passive peaking circuit peaks the electrical drive signal being delivered from the light source driver circuit to the light source, thereby widening the eye opening.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 4, 2015
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd
    Inventor: Vadim Heyfitch