Abstract: Embodiments herein relate to an apparatus and method for calibrating a notch filter which filters a power supply signal for a voltage-controlled oscillator (VCO). In one aspect, a control circuit performs a number of calibration cycles for the filter to determine a value of a calibration code for the filter which minimizes a change in a frequency of the output signal of the VCO due to a change in the voltage of the power supply signal. After each calibration cycle, the calibration code is adjusted based on whether the frequency of the output signal increase or decreases. The calibration cycles can therefore converge on an optimal calibration code which minimizes the change in frequency due to the change in voltage. This minimizes a sensitivity of the VCO to noise in the power supply signal.

Abstract: Described is an apparatus comprising a first circuitry, a second circuitry, a first capacitor array, and a second capacitor array. The first circuitry may have an oscillator. The first capacitor array may have a set of first capacitors to tune the oscillator. The second capacitor array may have a second capacitor to tune the oscillator. A capacitance of the second capacitor may be greater than an average capacitance of the first capacitors. The second circuitry may be operable to synchronously activate the second capacitor and deactivate a number N of the first capacitors, and to synchronously deactivate the second capacitor and activate the N first capacitors, based on a predetermined sequence.

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

Abstract: Methods for optimizing the atrio-ventricular (A-V) delay for efficacious delivery of cardiac resynchronization therapy. In CRT devices, the programmed A-V delay starts with detection of electrical activity in the right atrium (RA). Thus, a major component of the A-V delay is the time required for inter-atrial conduction time (IACT) from the RA to the LA. This IACT can be measured during implantation as the time from the atrial lead stimulation artifact to local electrograms in a coronary sinus (CS) catheter. Assuming that the beginning of LA contraction closely corresponds with the beginning of LA electrical activity, the optimal AV delay should be related to the time between the start of RA electrical activity and the start of LA electrical activity plus the duration of LA atrial contraction. Thus ‘during atrial pacing’ the IACT measured at implantation is correlated with the echocardiographically defined optimal paced AV delay (PAV).

Abstract: The linear fan comprises blades that are fixed onto a flexible transmission engaging leading and follower pulleys. Each blade has cylindrical shanks to facilitate swivel fixation. The veer of the blades is provided with directive disks.

Abstract: The linear fan comprises blades that are fixed onto a flexible transmission engaging leading and follower pulleys. Each blade has cylindrical shanks to facilitate swivel fixation. The veer of the blades is provided with directive disks. In another embodiment, position of the blades is permanent with respect to direction of motion of the transmissions and connection of the blades with the transmissions is provided with prismatic shanks in such a way that outlines of cross section of the blades are symmetrical with respect to direction of motion of the transmission. This fan also comprises the guide vanes that are fixed in one of two positions, the first position provides forward direction of operation and the second one assures reverse operation of the fan.

Abstract: Herein provided are methods for optimizing the atrio-ventricular (A-V) delay for efficacious delivery of cardiac resynchronization therapy. The A-V delay is set such that pacing-induced left ventricular contraction occurs following completion of left atrial (LA) contraction. This maximizes left ventricular filling (preload) which theoretically results in optimal LV contraction via the Frank-Starling mechanism. In CRT devices, the programmed A-V delay starts with detection of electrical activity in the right atrium (RA). Thus, a major component of the A-V delay is the time required for inter-atrial conduction time (IACT) from the RA to the LA. This IACT can be measured during implantation as the time from the atrial lead stimulation artifact to local electrograms in a coronary sinus (CS) catheter.