Abstract: A system and method of implementing asynchronous completion notification in an RDMA (remote data memory access) network interface card (RNIC). The method includes the steps of: storing a first CQE number of a most recent CQE placed into the CQ; storing a second CQE number of a most recent CQE retrieved from the CQ; issuing a request for completion notification; packaging the second CQE number with the request; and processing the request, wherein the processing step compares the first CQE number with the second CQE number to determine whether asynchronous completion notification should be immediately performed.

Abstract: A system and method for maintaining ordering in completion and retransmit operations in an RDMA environment. A system is provided for handling a completion process in an remote data memory access (RDMA) environment having a RequestOut channel and a ResponseOut channel, comprising: a descriptor list for each channel, wherein each descriptor list includes a message descriptor for each message in the channel; an update mechanism for updating a message length field in the message descriptor with a sequence number of a last byte in the message whenever a channel swap occurs between the RequestOut channel and the ResponseOut channel; an acknowledgement (Ack) completion system that examines values in a completion context and compares a sequence number of a next to complete message with a last acknowledged sequence number to determine if the message should be completed; and a read request completion system that performs completion of a read request.

Abstract: A system having a plurality of PCI devices, a PCI bus, a host system with a host memory, an network, and a target channel adpater. The plurality of PCI devices are attached to the PCI bus, which is connected via the target channel adpater and the network to the host system. The target channel adpater translates PCI bus transactions and PCI bus interrupts into network requests and network requests to PCI transactions. Each of the PCI devices has a PCI address range associated with it. A PCI memory window is allocated on the target channel adpater and is assigned to the host system. The PCI devices are enabled to post a pseudo address that belongs to the target channel adpater on the PCI bus when reading data via the network from the host memory or when writing data in the host memory via the network, the pseudo address comprising a base part (VABase) and an offset part (Offset).