Patents by Inventor Vadim MOSHINSKY

Vadim MOSHINSKY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CTLE adaptation based on statistical analysis
    Patent number: 11582074
    Abstract: Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process. The received signal is repeatedly sampled by an analog-to-digital converter (ADC). Certain samples containing interference that cannot be cancelled by a CTLE in the sampled series are filtered out (discarded). The remaining samples are used to generate, over a selected evaluation window, a histogram of the sampled values. This histogram is used to calculate a figure of merit for the current CTLE parameter settings. The figures of merit for various CTLE parameter settings are compared to find the set of CTLE parameter settings that optimize the figure of merit and by extension, optimize the CTLE circuitry's performance at equalizing the received signal.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: February 14, 2023
    Assignee: Rambus Inc.
    Inventors: Nanyan Wang, Vadim Moshinsky, Prashant Choudhary
  • CTLE ADAPTATION BASED ON STATISTICAL ANALYSIS
    Publication number: 20220217025
    Abstract: Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process. The received signal is repeatedly sampled by an analog-to-digital converter (ADC). Certain samples containing interference that cannot be cancelled by a CTLE in the sampled series are filtered out (discarded). The remaining samples are used to generate, over a selected evaluation window, a histogram of the sampled values. This histogram is used to calculate a figure of merit for the current CTLE parameter settings. The figures of merit for various CTLE parameter settings are compared to find the set of CTLE parameter settings that optimize the figure of merit and by extension, optimize the CTLE circuitry's performance at equalizing the received signal.
    Type: Application
    Filed: January 14, 2022
    Publication date: July 7, 2022
    Inventors: Nanyan WANG, Vadim MOSHINSKY, Prashant CHOUDHARY
  • CTLE adaptation based on statistical analysis
    Patent number: 11258641
    Abstract: Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process. The received signal is repeatedly sampled by an analog-to-digital converter (ADC). Certain samples containing interference that cannot be cancelled by a CTLE in the sampled series are filtered out (discarded). The remaining samples are used to generate, over a selected evaluation window, a histogram of the sampled values. This histogram is used to calculate a figure of merit for the current CTLE parameter settings. The figures of merit for various CTLE parameter settings are compared to find the set of CTLE parameter settings that optimize the figure of merit and by extension, optimize the CTLE circuitry's performance at equalizing the received signal.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: February 22, 2022
    Assignee: Rambus Inc.
    Inventors: Nanyan Wang, Vadim Moshinsky, Prashant Choudhary
  • CTLE ADAPTATION BASED ON STATISTICAL ANALYSIS
    Publication number: 20210281449
    Abstract: Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process. The received signal is repeatedly sampled by an analog-to-digital converter (ADC). Certain samples containing interference that cannot be cancelled by a CTLE in the sampled series are filtered out (discarded). The remaining samples are used to generate, over a selected evaluation window, a histogram of the sampled values. This histogram is used to calculate a figure of merit for the current CTLE parameter settings. The figures of merit for various CTLE parameter settings are compared to find the set of CTLE parameter settings that optimize the figure of merit and by extension, optimize the CTLE circuitry's performance at equalizing the received signal.
    Type: Application
    Filed: February 22, 2021
    Publication date: September 9, 2021
    Inventors: Nanyan WANG, Vadim MOSHINSKY, Prashant CHOUDHARY