Patents by Inventor Vadim Smolyakov
Vadim Smolyakov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190139584Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.Type: ApplicationFiled: December 31, 2018Publication date: May 9, 2019Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
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Patent number: 10176850Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.Type: GrantFiled: January 26, 2018Date of Patent: January 8, 2019Assignee: Maxlinear, Inc.Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
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Publication number: 20180151202Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.Type: ApplicationFiled: January 26, 2018Publication date: May 31, 2018Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
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Patent number: 9881653Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.Type: GrantFiled: February 16, 2017Date of Patent: January 30, 2018Assignee: Maxlinear, Inc.Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
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Publication number: 20170162233Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.Type: ApplicationFiled: February 16, 2017Publication date: June 8, 2017Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
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Patent number: 9576614Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.Type: GrantFiled: August 4, 2014Date of Patent: February 21, 2017Assignee: MAXLINEAR, INC.Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
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Patent number: 9165677Abstract: A plurality of data lines and a plurality of bit lines may be used to write to and/or read from an array of memory cells. A switching element may select among different mappings between the plurality of data lines and the plurality of bit lines. The array may, for example, consist of N memory cells, the plurality of bit lines may consist of N bit lines, and the plurality of data lines may consist of N data lines, where N is an integer greater than 1. For a write operation in which a data block is to be written to the array, a configuration of the switching element may be controlled based, at least in part, on how sensitive the data block is to a faulty memory cell among the array of memory cells.Type: GrantFiled: October 31, 2011Date of Patent: October 20, 2015Assignee: MAXLINEAR, INC.Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
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Publication number: 20150023122Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.Type: ApplicationFiled: August 4, 2014Publication date: January 22, 2015Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
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Patent number: 8897086Abstract: One or more circuits may comprise an array of memory cells corresponding to a particular memory address, and a memory fault mitigation module. The one or more circuits may be operable to write a data block to the array of memory cells. The write operation may comprises a swap of a first portion of the data block with a second portion of the data block in response to a detection that one or more memory cells of the array is faulty, and storing the data block to the array of memory cells after the swap.Type: GrantFiled: February 4, 2013Date of Patent: November 25, 2014Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
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Patent number: 8797813Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.Type: GrantFiled: October 31, 2011Date of Patent: August 5, 2014Assignee: MaxLinear, Inc.Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
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Patent number: 8705298Abstract: One or more circuits may include an array of memory cells corresponding to a particular memory address. The one or more circuits may be operable to discover a location of a faulty memory cell in the array of memory cells. The one or more circuits may be operable to arrange the order in which the bits of a data block are stored to said array of memory cells based, at least in part, on said discovered location of said faulty memory cell.Type: GrantFiled: February 4, 2013Date of Patent: April 22, 2014Assignee: MaxLinear, Inc.Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
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Publication number: 20130141996Abstract: One or more circuits may comprise an array of memory cells corresponding to a particular memory address, and a memory fault mitigation module. The one or more circuits may be operable to write a data block to the array of memory cells. The write operation may comprises a swap of a first portion of the data block with a second portion of the data block in response to a detection that one or more memory cells of the array is faulty, and storing the data block to the array of memory cells after the swap.Type: ApplicationFiled: February 4, 2013Publication date: June 6, 2013Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
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Publication number: 20130141995Abstract: One or more circuits may include an array of memory cells corresponding to a particular memory address. The one or more circuits may be operable to discover a location of a faulty memory cell in the array of memory cells. The one or more circuits may be operable to arrange the order in which the bits of a data block are stored to said array of memory cells based, at least in part, on said discovered location of said faulty memory cell.Type: ApplicationFiled: February 4, 2013Publication date: June 6, 2013Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
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Publication number: 20120294094Abstract: A plurality of data lines and a plurality of bit lines may be used to write to and/or read from an array of memory cells. A switching element may select among different mappings between the plurality of data lines and the plurality of bit lines. The array may, for example, consist of N memory cells, the plurality of bit lines may consist of N bit lines, and the plurality of data lines may consist of N data lines, where N is an integer greater than 1. For a write operation in which a data block is to be written to the array, a configuration of the switching element may be controlled based, at least in part, on how sensitive the data block is to a faulty memory cell among the array of memory cells.Type: ApplicationFiled: October 31, 2011Publication date: November 22, 2012Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
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Publication number: 20120294100Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.Type: ApplicationFiled: October 31, 2011Publication date: November 22, 2012Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak