Abstract: Reducing noise from drive tone and sense resonance peaks of a micro-electro-mechanical system (MEMS) gyroscope output using a notch filter is presented herein. The MEMS gyroscope can include a drive oscillation component configured to vibrate a sensor mass at a drive resonance frequency; a sense circuit configured to detect a deflection of the sensor mass, and generate, based on the deflection and the drive resonance frequency, a demodulated output; and a signal processing component configured to receive a set of frequencies comprising a first value representing the drive resonance frequency and a second value corresponding to a sense resonance frequency associated with the sense circuit, and apply, based on the first value and the second value, a notch filter to the demodulated output to obtain a filtered output.

Abstract: Reducing noise from drive tone and sense resonance peaks of a micro-electro-mechanical system (MEMS) gyroscope output using a notch filter is presented herein. The MEMS gyroscope can include a drive oscillation component configured to vibrate a sensor mass at a drive resonance frequency; a sense circuit configured to detect a deflection of the sensor mass, and generate, based on the deflection and the drive resonance frequency, a demodulated output; and a signal processing component configured to receive a set of frequencies comprising a first value representing the drive resonance frequency and a second value corresponding to a sense resonance frequency associated with the sense circuit, and apply, based on the first value and the second value, a notch filter to the demodulated output to obtain a filtered output.

Abstract: A MEMS device and method for amplitude regulation of a MEMS device are disclosed. In a first aspect, the MEMS device comprises a MEMS resonator, a limiter coupled to the MEMS resonator, and a regulator coupled to the limiter. The MEMS device includes an amplitude control circuit coupled to the MEMS resonator. The amplitude control circuit controls a supply of the limiter via the regulator to regulate oscillation loop amplitude of the MEMS device. In a second aspect, the method includes coupling a regulator to the limiter, coupling an amplitude control circuit to the MEMS resonator, and controlling a supply of the limiter via the regulator to regulate oscillation loop amplitude of the MEMS device.

Abstract: A MEMS device and method for amplitude regulation of a MEMS device are disclosed. In a first aspect, the MEMS device comprises a MEMS resonator, a limiter coupled to the MEMS resonator, and a regulator coupled to the limiter. The MEMS device includes an amplitude control circuit coupled to the MEMS resonator. The amplitude control circuit controls a supply of the limiter via the regulator to regulate oscillation loop amplitude of the MEMS device. In a second aspect, the method includes coupling a regulator to the limiter, coupling an amplitude control circuit to the MEMS resonator, and controlling a supply of the limiter via the regulator to regulate oscillation loop amplitude of the MEMS device.

Abstract: A testing device for testing a high-speed serial transmitter or other device includes an input stage having a first comparator, a second comparator, and a digital-to-analog converter. The first comparator compares first differential signals from a device under test. The second comparator compares the first differential signals and second differential signals from the digital-to-analog converter. An analysis unit identifies first beats based on an output of the first comparator and second beats based on an output of the second comparator. The analysis unit identifies one or more characteristics of the device under test (such as jitter, differential signal swing, and transition time) based on the first and second beats. A clock unit provides an adjustable clock signal to the comparators. The clock signal may have a frequency shift with respect to a frequency of the device under test.

Abstract: An integrated circuit in accordance with one embodiment of the invention includes an oscillator circuit and a source circuit. The source circuit outputs a reference voltage and a bias current, wherein the reference voltage changes by substantially the same proportion as the bias current. The oscillator circuit is coupled to receive the reference voltage and the bias current from the source circuit. The oscillator circuit outputs an oscillating electrical signal.

Abstract: An apparatus and method for noise reduction in a successive approximation (SA) analog-to-digital converter (ADC) is provided. The SA ADC includes a noise-compensating comparator circuit, an SA logic circuit, and a DAC circuit. A first reference signal is generated such that the first reference signal has a noise component that is substantially similar to a noise component of a first comparison signal. The noise-compensated comparator circuit is configured to provide a differential signal. The first comparison signal is included in a first half of the differential signal, and the first reference signal is included in a second half of the differential signal, such that the noise component of the first comparison signal is substantially cancelled out differentially. The noise-compensating comparator circuit is further configured to compare the two halves of the differential signal to provide a comparator output signal.

Abstract: A network line equalizer includes a transconductance-controlled, tunable single zero high-pass, filter that includes a single zero impedance circuit, and first and second MOS transistors that output differential currents based on differential input signals and the impedance of the single zero impedance circuit. The MOS transistors act as source followers to convert the differential input voltage signals to respective differential current signals. The single zero impedance circuit connects the first and second MOS transistors, and causes the first and second MOS transistors to output a corrected pair of differential signals based on the impedance. The impedance of the single zero IMPEDANCE circuit is implemented using CMOS transistors, enabling the impedance to be dynamically controlled by an external impedance controller.

Abstract: A phase comparator for comparing the relative phase of a first input signal and a second input signal. The phase comparator detects a slipping condition, the slipping condition present if the first input signal leads the second input signal in phase and the first input signal is delayed for at least one cycle such that a first rising edge of the first input signal lags a first rising edge of the second input signal by greater than 180°. The phase detector resets at least one output of the phase comparator upon the detection of the slipping condition. Also described are circuits to implement the phase comparator and a transconductance compensation circuit for a filter, and methods of comparing phase and transconductance compensation.

Abstract: A filter compensating circuit having a sine wave generator, the sine wave generator generating a sine wave; a filter coupled to the sine wave generator and delaying a phase of the sine wave; a filter sine to square wave converter coupled to the filter and converting the delayed sine wave into a filter square wave signal; a reference sine to square wave converter coupled to the sine wave generator and converting the sine wave into a reference square wave signal; a comparator coupled to the filter sine to square wave converter and to the reference sine to square wave converter, the comparator comparing a phase relationship between the filter square wave signal and the reference square wave filter; and a correction signal generator coupled to the comparator, the correction signal generator generating a correction signal based on the comparison of the phase relationship, the correction signal being feedback to the filter to adjust a transconductance of the filter.

Abstract: A network line equalizer includes a transconductance-controlled, tunable single zero, single pole filter that eliminates the necessity of feedback loops or operational amplifiers. The equalizer includes a first MOS transistor having a first size (S1) and a gate for receiving input voltage signal and in response outputting a first current signal. A low pass filter composed of MOS transistors outputs a filtered voltage signal, and a second MOS transistor converts the filtered voltage signal to a second current signal. The second MOS transistor has a size (S2) relative to the first size (S1) such that S2=S1 (z-p)/p, where z is the zero and p is the pole of the filter. The circuit can be duplicated for filtering of differential input voltage signals, where the four current signals can be selectively combined based on whether the zero is at a lower frequency than the pole.

Abstract: A network line equalizer is provided in combination with a compensation circuit. The network line equalizer includes first and second nodes, first and second current sources respectively connected to the first and second nodes, first and second transistors respectively connected also to the first and second nodes with a gate of the first transistor receiving a first signal of a differential pair of transmitted signals and a gate of the second transistor receiving a second signal of the differential pair of transmitted signals, a third transistor connected between the first and second nodes, and a control line connected to a gate of the third transistor.

Abstract: A network line equalizer includes a transconductance-controlled, tunable single zero high pass filter having a parasitic pole, and a single zero, single pole low pass filter, that eliminates the necessity of feedback loops or operational amplifiers. The tunable single zero high-pass filter includes a single zero impedance circuit, and first and second MOS transistors that output differential currents based on differential input signals and the impedance of the single zero impedance circuit. The MOS transistors act as source followers to convert the differential input voltage signals to respective differential current signals. The single zero impedance circuit connects the first and second MOS transistors, and causes the first and second MOS transistors to output a filtered pair of differential signals based on the impedance. The impedance of the single zero impedance circuit is implemented using CMOS transistors, enabling the impedance to be dynamically controlled by an external impedance controller.

Abstract: An output driver circuit for use with ethernet repeaters is disclosed which produces a symmetric (low jitter) output signal in response to an input signal. The circuit further exhibits low ground bounce by maintaining an output level swing of between 1.5 and 1.8 volts. When not transmitting, the driver provides power savings by maintaining a half level signal at its output.