Abstract: A method and a device for translating a hierarchical address, the device is adapted to receive a destination address, to search an array of sorted binary string being associated with a group of addresses reachable through the device, and to provide a best matching address, the device comprising: a content addressable memory module, for storing a first portion of the array of sorted binary strings; a fast memory module, for storing a second portion of the sorted binary strings; a memory module, for storing a remaining portion of the tree of sorted strings; and a search engine, coupled to the content addressable memory unit module, the fast memory module and the memory module, configured to receive a destination address, access at least the fast memory unit and the memory unit and to find the best matching address.

Abstract: A communication system (300) comprises interfaces (311-314) at communication channels (361-364, respectively), coupled to a controller (340) by an address bus (320) and multiplexer (380). The interfaces (311-314) receive data cells and provide status signals (e.g., clav) indicating, for example, cell availability, independently from interface addresses (ADDR) being present at the address bus (320). The interfaces (311-314) continuously send the status signals to the multiplexer (380) which receives the interface address (ADDR) at a control input (386) and forwards the status information of the currently addressed interface to the controller (340).

Abstract: A communication system (600) has a first processor (210) and a second processor (220). The first processor (210) has a first number of address bits (e.g., A=5) to select a first device (651), and the second processor (220) has a second number of address bits (e.g., B=4 to select a second device (661). The processors (210, 220) are coupled to the devices (651, 661) by a shared bus (640) with a total number of bit lines (641-648) which is smaller than or equal to the sum of the first and second numbers of bits (e.g., N=8). The bit lines (641-648) are assigned to a first outer set (641-643), a second outer set (646-648) and to an inner set (644-645). LSB-bits from the first processor (210) are coupled to the first outer set (641-643), LSB-bits from the second processor (220) are coupled to the second outer set (646-648), and MSB-bit of first and second processors (210, 220) are multiplexed to the lines of the inner set (644-645).