Patents by Inventor Vage Oganesian

Vage Oganesian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804151
    Abstract: In interconnect fabrication (e.g. a damascene process), a barrier layer (possibly conductive) is formed over a substrate with holes, a conductor is formed over the barrier layer, and the conductor and the barrier layer are polished to expose the substrate around the holes and provide interconnect features in the holes. To prevent erosion/dishing of the conductor over the holes, the conductor is covered by another, “first” layer before polishing; then the first layer, the conductor, and the barrier layer are polished to expose the substrate. The first layer may or may not be conductive. The first layer protects the conductor to reduce or eliminate the conductor erosion/dishing over the holes.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: October 13, 2020
    Assignee: Tessera, Inc.
    Inventors: Cyprian Emeka Uzoh, Vage Oganesian, Ilyas Mohammed
  • Patent number: 10559494
    Abstract: A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: February 11, 2020
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Craig Mitchell, Ilyas Mohammed, Piyush Savalia
  • Patent number: 10354942
    Abstract: A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: July 16, 2019
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Publication number: 20190131387
    Abstract: A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.
    Type: Application
    Filed: December 13, 2018
    Publication date: May 2, 2019
    Applicant: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Piyush Savalia
  • Patent number: 10262947
    Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect an additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: April 16, 2019
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Ilyas Mohammed, Craig Mitchell, Belgacem Haba, Piyush Savalia
  • Patent number: 10199275
    Abstract: In interconnect fabrication (e.g. a damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect features in the holes. To prevent erosion/dishing of the conductive layer at the holes, the conductive layer is covered by a sacrificial layer (possibly conformal) before polishing; then both layers are polished. Initially, before polishing, the conductive layer and the sacrificial layer are recessed over the holes, but the sacrificial layer is polished at a lower rate to result in a protrusion of the conductive layer at a location of each hole. The polishing can continue to remove the protrusions and provide a planar surface.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: February 5, 2019
    Assignee: TESSERA, INC.
    Inventors: Cyprian Uzoh, Vage Oganesian, Ilyas Mohammed
  • Patent number: 10199519
    Abstract: A sensor device includes a first substrate of semiconductor material having opposing first and second surfaces, photodetectors configured to receive light impinging on the first surface, and first contact pads each exposed at both the first and second surfaces and electrically coupled to at least one of the photodetectors. A second substrate comprises opposing first and second surfaces, electrical circuits, a second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits, and a plurality of cooling channels formed as first trenches extending into the second surface of the second substrate but not reaching the first surface of the second substrate. The first substrate second surface is mounted to the second substrate first surface such that each of the first contact pads is electrically coupled to at least one of the second contact pads.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: February 5, 2019
    Assignee: OPTIZ, INC.
    Inventors: Vage Oganesian, Zhenhua Lu
  • Patent number: 10157978
    Abstract: A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: December 18, 2018
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Piyush Savalia
  • Patent number: 10139619
    Abstract: An image sensor that includes a substrate having front and back surfaces, a plurality of photo detectors formed adjacent the front surface, a plurality of contact pads at the front surface and electrically coupled to the photo detectors, and a plurality of light manipulation components disposed on a portion of the back surface. The photo detectors are configured to generate electrical signals in response to light incident through the light manipulation components and through the portion of the back surface. The portion of the back surface has a non-planar shape.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: November 27, 2018
    Assignee: OPTIZ, INC.
    Inventors: Vage Oganesian, Zhenhua Lu
  • Publication number: 20180254213
    Abstract: A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.
    Type: Application
    Filed: May 4, 2018
    Publication date: September 6, 2018
    Applicant: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Craig Mitchell, Ilyas Mohammed, Piyush Savalia
  • Publication number: 20180226517
    Abstract: A sensor device includes a first substrate of semiconductor material having opposing first and second surfaces, photodetectors configured to receive light impinging on the first surface, and first contact pads each exposed at both the first and second surfaces and electrically coupled to at least one of the photodetectors. A second substrate comprises opposing first and second surfaces, electrical circuits, a second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits, and a plurality of cooling channels formed as first trenches extending into the second surface of the second substrate but not reaching the first surface of the second substrate. The first substrate second surface is mounted to the second substrate first surface such that each of the first contact pads is electrically coupled to at least one of the second contact pads.
    Type: Application
    Filed: April 3, 2018
    Publication date: August 9, 2018
    Inventors: Vage Oganesian, Zhenhua Lu
  • Patent number: 10032646
    Abstract: An interconnect element 130 can include a dielectric layer 116 having a top face 116b and a bottom face 116a remote from the top face, a first metal layer defining a plane extending along the bottom face and a second metal layer extending along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces 132, 134. A plurality of conductive protrusions 112 can extend upwardly from the plane defined by the first metal layer 102 through the dielectric layer 116. The conductive protrusions 112 can have top surfaces 126 at a first height 115 above the first metal layer 132 which may be more than 50% of a height of the dielectric layer. A plurality of conductive vias 128 can extend from the top surfaces 126 of the protrusions 112 to connect the protrusions 112 with the second metal layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: July 24, 2018
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Vage Oganesian, Kimitaka Endo
  • Patent number: 9996725
    Abstract: A sensor assembly that includes a silicon substrate and a sensor integrally formed on or in its top surface. Bond pads are formed at the substrate top surface and electrically coupled to the sensor. A trench is formed into the top surface, extending toward but not reaching the substrate's bottom surface. Conductive first traces each extend from one of the bond pads and down into the trench. One or more holes are formed into the bottom surface of the substrate and extend toward but do not reach the top surface. The one or more holes terminate at the bottom of the trench in a manner exposing the conductive first traces. Conductive second traces each extend from one of the conductive first traces at the bottom of the trench, along a sidewall of the one or more holes, and along the bottom surface of the silicon substrate.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: June 12, 2018
    Assignee: Optiz, Inc.
    Inventor: Vage Oganesian
  • Patent number: 9985063
    Abstract: An imaging device that includes an array of photo detectors each configured to generate an electrical signal in response to received light, and an array of color filters disposed over the array of photo detectors such that the photo detectors receive light passing through the color filters. Each of the color filters has a color transmission characteristic, which vary. To even out color balance, some of the color filters are disposed over a plurality of the photo detectors while others are disposed over only one of the photo detectors. Additional color balance can be achieved by varying the relative area sizes of the color filters and underlying photo detectors based on color transmission characteristics, to compensate for the varying absorption coefficient of the photo detectors at different colors.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: May 29, 2018
    Assignee: Optiz, Inc.
    Inventors: Vage Oganesian, Zhenhua Lu
  • Patent number: 9972730
    Abstract: A sensor device includes a first substrate of semiconductor material having opposing first and second surfaces, photodetectors configured to receive light impinging on the first surface, and first contact pads each exposed at both the first and second surfaces and electrically coupled to at least one of the photodetectors. A second substrate comprises opposing first and second surfaces, electrical circuits, a second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits, and a plurality of cooling channels formed as first trenches extending into the second surface of the second substrate but not reaching the first surface of the second substrate. The first substrate second surface is mounted to the second substrate first surface such that each of the first contact pads is electrically coupled to at least one of the second contact pads.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: May 15, 2018
    Assignee: Optiz, Inc.
    Inventors: Vage Oganesian, Zhenhua Lu
  • Publication number: 20180130746
    Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.
    Type: Application
    Filed: November 27, 2017
    Publication date: May 10, 2018
    Inventors: Vage OGANESIAN, Ilyas MOHAMMED, Craig MITCHELL, Belgacem HABA, Piyush SAVALIA
  • Patent number: 9966303
    Abstract: A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: May 8, 2018
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Craig Mitchell, Ilyas Mohammed, Piyush Savalia
  • Publication number: 20180121705
    Abstract: A sensor assembly that includes a silicon substrate and a sensor integrally formed on or in its top surface. Bond pads are formed at the substrate top surface and electrically coupled to the sensor. A trench is formed into the top surface, extending toward but not reaching the substrate's bottom surface. Conductive first traces each extend from one of the bond pads and down into the trench. One or more holes are formed into the bottom surface of the substrate and extend toward but do not reach the top surface. The one or more holes terminate at the bottom of the trench in a manner exposing the conductive first traces. Conductive second traces each extend from one of the conductive first traces at the bottom of the trench, along a sidewall of the one or more holes, and along the bottom surface of the silicon substrate.
    Type: Application
    Filed: November 3, 2016
    Publication date: May 3, 2018
    Inventor: Vage Oganesian
  • Publication number: 20180114743
    Abstract: A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.
    Type: Application
    Filed: December 14, 2017
    Publication date: April 26, 2018
    Applicant: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Publication number: 20180102286
    Abstract: In interconnect fabrication (e.g. a damascene process), a barrier layer (possibly conductive) is formed over a substrate with holes, a conductor is formed over the barrier layer, and the conductor and the barrier layer are polished to expose the substrate around the holes and provide interconnect features in the holes. To prevent erosion/dishing of the conductor over the holes, the conductor is covered by another, “first” layer before polishing; then the first layer, the conductor, and the barrier layer are polished to expose the substrate. The first layer may or may not be conductive. The first layer protects the conductor to reduce or eliminate the conductor erosion/dishing over the holes.
    Type: Application
    Filed: December 7, 2017
    Publication date: April 12, 2018
    Applicant: TESSERA, INC.
    Inventors: Cyprian UZOH, Vage OGANESIAN, Ilyas MOHAMMED