Patents by Inventor Vaibhav Amarayya Hiremath

Vaibhav Amarayya Hiremath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sync point mechanism between master and slave nodes
    Patent number: 11604655
    Abstract: In a system with a master processor and slave processors, sync points are used in boot instructions. While executing the boot instructions, the slave processor determines whether the sync point is enabled. In response to determining the sync point is enabled, the slave processor pauses execution of the boot instructions, waits for commands from the master processor, receives commands from the master processor, executes the received commands until a release command is received, and then continues to execute boot instructions. In response to determining the sync point is not enabled, the slave processor continues to execute boot instructions.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: March 14, 2023
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Wentao Xu, Randall Alexander Brown, Vaibhav Amarayya Hiremath, Shijie Che, Kamraan Nasim
  • Master-Slave Communication with Subdomains
    Publication number: 20220335003
    Abstract: A computing system may implement a method for creating a first subdomain by configuring one of a first plurality of slave nodes as a first subdomain master node and configuring one or more other slave nodes of the first plurality of slave nodes as first subdomain slave nodes to the first subdomain master node.
    Type: Application
    Filed: April 19, 2021
    Publication date: October 20, 2022
    Inventors: Shijie Che, Wentao Xu, Randall Brown, Vaibhav Amarayya Hiremath, Manuchehr Taghi-Loo
  • SYNC POINT MECHANISM BETWEEN MASTER AND SLAVE NODES
    Publication number: 20220147366
    Abstract: In a system with a master processor and slave processors, sync points are used in boot instructions. While executing the boot instructions, the slave processor determines whether the sync point is enabled. In response to determining the sync point is enabled, the slave processor pauses execution of the boot instructions, waits for commands from the master processor, receives commands from the master processor, executes the received commands until a release command is received, and then continues to execute boot instructions. In response to determining the sync point is not enabled, the slave processor continues to execute boot instructions.
    Type: Application
    Filed: November 12, 2020
    Publication date: May 12, 2022
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Wentao Xu, Randall Alexander Brown, Vaibhav Amarayya Hiremath, Shijie Che, Kamraan Nasim