Patents by Inventor Vaibhav Dinesh
Vaibhav Dinesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170059687Abstract: Examples of systems and methods for estimating a device location are disclosed. In one example, a device locating system includes three or more sensor devices, a processor, and a storage device storing instructions executable to determine an estimated location of a scanned device based on a received signal strength indication (RSSI) value for the scanned device measured by at least three of the three or more sensor devices and processed in view of previously-recorded RSSI values for the scanned device. The instructions are further executable to output the estimated location of the scanned device to a computing device for controlling operation of the computing device.Type: ApplicationFiled: February 29, 2016Publication date: March 2, 2017Inventors: Vaibhav Dinesh, Prakash Tripathi, Ajit Singh
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Patent number: 9178990Abstract: Systems and methods for characterizing loops based on frequency domain reflectometry single-ended line testing (FDR-SELT) are described. One embodiment includes a method for determining whether a straight-loop departure condition exists on a loop under test. First, an un-calibrated echo signal is received. A region associated with the loop under test, a platform type, and estimated the length of the loop under test are then used together with the received un-calibrated echo signal to determine whether the loop is not a straight loop is determined through determining whether at least one differentiating feature is present in the received signal. Another embodiment includes a method for determining a loop gauge for a loop under test through analyzing characteristics relating to local maxima and local minima of the received un-calibrated echo signal using the region, platform type, and the estimated loop length.Type: GrantFiled: June 30, 2008Date of Patent: November 3, 2015Assignee: IKANOS COMMUNICATIONS, INC.Inventors: Vaibhav Dinesh, Kunal Raheja, Patrick Duvaut
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Patent number: 8515017Abstract: Systems and methods for performing loop termination are described. One embodiment is a method that comprises receiving a per-port calibrated echo signal of a loop under test, receiving a region designation and a loop length for the loop under test, and determining whether the loop is terminated by a short or open termination based on phase of the per-port calibrated echo signal.Type: GrantFiled: March 7, 2008Date of Patent: August 20, 2013Assignee: Ikanos Communications, Inc.Inventors: Patrick Duvaut, Amitkumar Mahadevan, Vaibhav Dinesh
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Patent number: 8515016Abstract: Systems and methods for performing bridge tap detection are described. One embodiment is a method which comprises receiving an echo signal for a loop under test where the echo signal is a per-port calibrated echo response obtained using frequency domain reflectometry single-ended line testing (FDR-SELT). The method further comprises analyzing the echo signal to determine whether differentiating features are present in the per-port calibrated echo signal in order to determine whether the loop under test is a bridge tapped loop.Type: GrantFiled: March 7, 2008Date of Patent: August 20, 2013Assignee: Ikanos Communications, Inc.Inventors: Patrick Duvaut, Amitkumar Mahadevan, Vaibhav Dinesh
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Patent number: 8509389Abstract: Systems and methods for performing loop length estimation are described. One embodiment includes a method which comprises receiving an echo signal for a loop under test where the echo signal is a per-port calibrated echo response obtained using frequency domain reflectometry single-ended line testing (FDR-SELT). The method further comprises analyzing characteristics of the echo signal to perform a loop length estimation based on data relating to ripple frequency as a function of loop length.Type: GrantFiled: March 7, 2008Date of Patent: August 13, 2013Assignee: Ikanos Communications, Inc.Inventors: Patrick Duvaut, Amitkumar Mahadevan, Vaibhav Dinesh
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Patent number: 8300771Abstract: Disclosed are various embodiments for determining a state of loop termination. One embodiment comprises receiving an un-calibrated echo signal for the loop under test using frequency domain reflectometry single-ended line testing (FDR-SELT) and determining the state of loop termination based on phase of the un-calibrated echo signal. The step of determining the state of loop termination comprises determining whether the loop is terminated by an open termination or a short termination by correlating the phase of the echo signal with an expected phase of the echo signal derived from measurements taken at the same loop length for open and short terminations. For other embodiments, the amplitude of the un-calibrated echo signal is analyzed to determine whether the loop is terminated by a matched-impedance termination.Type: GrantFiled: December 1, 2008Date of Patent: October 30, 2012Assignee: Ikanos Communications, Inc.Inventors: Vaibhav Dinesh, Kunal Raheja, Amitkumar Mahadevan, Patrick Duvaut
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Patent number: 8295444Abstract: Systems and methods for performing loop analysis are described. Some embodiments are directed to determining loop characteristics such as loop gauge, loop termination, and straight-loop departure. One embodiment includes a method for performing loop length estimation which comprises receiving an un-calibrated echo signal for a loop under test using frequency domain reflectometry single-ended line testing (FDR-SELT), a region associated with the loop under test, and a platform type. The method comprises classifying the loop under test and outputting a loop length estimate based on the classification of the loop under test and based on one of a ripple-period approach and a template-matching approach.Type: GrantFiled: June 13, 2008Date of Patent: October 23, 2012Assignee: Ikanos Communications, Inc.Inventors: Vaibhav Dinesh, Kunal Raheja, Patrick Duvaut
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Publication number: 20100086105Abstract: Disclosed are various embodiments for determining a state of loop termination. One embodiment comprises receiving an un-calibrated echo signal for the loop under test using frequency domain reflectometry single-ended line testing (FDR-SELT) and determining the state of loop termination based on phase of the un-calibrated echo signal. The step of determining the state of loop termination comprises determining whether the loop is terminated by an open termination or a short termination by correlating the phase of the echo signal with an expected phase of the echo signal derived from measurements taken at the same loop length for open and short terminations. For other embodiments, the amplitude of the un-calibrated echo signal is analyzed to determine whether the loop is terminated by a matched-impedance termination.Type: ApplicationFiled: December 1, 2008Publication date: April 8, 2010Applicant: CONEXANT SYSTEMS, INC.Inventors: Vaibhav Dinesh, Kunal Raheja, Amitkumar Mahadevan, Patrick Duvaut
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Publication number: 20090323902Abstract: Systems and methods for characterizing loops based on single-ended line test (SELT) are described. One embodiment includes a method for determining whether a straight-loop departure condition exists on a loop under test. In accordance with such embodiments, the method comprises receiving an un-calibrated echo signal for the loop under test using frequency domain reflectometry single-ended line testing (FDR-SELT), a region associated with the loop under test, a platform type, and a length of the loop under test. Based on the region, platform type, and loop length, the method further comprises determining whether the loop is not a straight loop, wherein determining whether the loop is not a straight loop comprises determining whether at least one differentiating feature is present in the un-calibrated echo signal. Another embodiment includes a method for determining a loop gauge for a loop under test.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Applicant: CONEXANT SYSTEMS, INC.Inventors: Vaibhav Dinesh, Kunal Raheja, Patrick Duvaut
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Publication number: 20090310755Abstract: Systems and methods for performing loop analysis are described. Some embodiments are directed to determining loop characteristics such as loop gauge, loop termination, and straight-loop departure. One embodiment includes a method for performing loop length estimation which comprises receiving an un-calibrated echo signal for a loop under test using frequency domain reflectometry single-ended line testing (FDR-SELT), a region associated with the loop under test, and a platform type. The method comprises classifying the loop under test and outputting a loop length estimate based on the classification of the loop under test and based on one of a ripple-period approach and a template-matching approach.Type: ApplicationFiled: June 13, 2008Publication date: December 17, 2009Applicant: CONEXANT SYSTEMS, INC.Inventors: Vaibhav Dinesh, Kunal Raheja, Patrick Duvaut
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Publication number: 20080298555Abstract: Systems and methods for performing loop length estimation are described. One embodiment includes a method which comprises receiving an echo signal for a loop under test where the echo signal is a per-port calibrated echo response obtained using frequency domain reflectometry single-ended line testing (FDR-SELT). The method further comprises analyzing characteristics of the echo signal to perform a loop length estimation based on data relating to ripple frequency as a function of loop length.Type: ApplicationFiled: March 7, 2008Publication date: December 4, 2008Applicant: CONEXANT SYSTEMS, INC.Inventors: Patrick Duvaut, Amitkumar Mahadevan, Vaibhav Dinesh
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Publication number: 20080279269Abstract: Systems and methods for performing loop termination are described. One embodiment is a method that comprises receiving a per-port calibrated echo signal of a loop under test, receiving a region designation and a loop length for the loop under test, and determining whether the loop is terminated by a short or open termination based on phase of the per-port calibrated echo signal.Type: ApplicationFiled: March 7, 2008Publication date: November 13, 2008Applicant: CONEXANT SYSTEMS, INC.Inventors: Patrick Duvaut, Amitkumar Mahadevan, Vaibhav Dinesh
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Publication number: 20080240368Abstract: Systems and methods for performing bridge tap detection are described. One embodiment is a method which comprises receiving an echo signal for a loop under test where the echo signal is a per-port calibrated echo response obtained using frequency domain reflectometry single-ended line testing (FDR-SELT). The method further comprises analyzing the echo signal to determine whether differentiating features are present in the per-port calibrated echo signal in order to determine whether the loop under test is a bridge tapped loop.Type: ApplicationFiled: March 7, 2008Publication date: October 2, 2008Applicant: CONEXANT SYSTEMS, INC.Inventors: Patrick Duvaut, Amitkumar Mahadevan, Vaibhav Dinesh
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Publication number: 20080219413Abstract: Systems and methods for performing loop gauge detection are described. One embodiment is a method that comprises receiving a calibrated per-port echo signal of a loop under test, receiving a loop length estimation for the loop under test, and estimating the loop gauge of the loop under test if the loop is not determined to be a long loop based on a predetermined threshold and if no bridge tap is present on the loop. In accordance with such embodiments, estimating the loop gauge of the loop under test is based on at least one of the following echo signal features: energy of the echo signal in a predetermined frequency band, information on an envelope of maxima for the echo signal, information on an envelope of minima for the echo signal, and a span of ripples on the amplitude of the echo signal.Type: ApplicationFiled: March 7, 2008Publication date: September 11, 2008Applicant: CONEXANT SYSTEMS, INC.Inventors: Patrick Duvaut, Amitkumar Mahadevan, Vaibhav Dinesh