Abstract: A time-interleaved circuit includes an input buffer, a plurality of track-and-hold circuits, and a plurality of isolation inductors. The input buffer is configured to receive an input signal having an input voltage and to output an output signal having an output voltage. The track-and-hold circuits are electrically coupled in parallel with each other. Each track-and-hold circuit is electrically coupled in series with the input buffer. Each isolation inductor is electrically coupled to the output of the input buffer and at least one of the track-and-hold circuits.

Abstract: A piecewise linear gain amplifier circuit includes a differential preamplifier and a plurality of transconductors. The differential preamplifier is electrically coupled to a differential input having an input voltage. The transconductors are electrically coupled in parallel with each other. Each transconductor includes a respective differential input that is electrically coupled to a differential output of the differential preamplifier. In addition, each transconductor includes a respective differential output that is electrically coupled to a common differential PWL output. Each transconductor has a different linear input range. An optional attenuation circuit can be electrically coupled in parallel to the differential preamplifier. The differential output of the attenuation circuit can be electrically coupled to a differential input of another transconductor, and that transconductor can have a differential output that is electrically coupled to the common differential PWL output.

Abstract: A time-interleaved circuit includes an input buffer, a plurality of track-and-hold circuits, and a plurality of isolation inductors. The input buffer is configured to receive an input signal having an input voltage and to output an output signal having an output voltage. The track-and-hold circuits are electrically coupled in parallel with each other. Each track-and-hold circuit is electrically coupled in series with the input buffer. Each isolation inductor is electrically coupled to the output of the input buffer and at least one of the track-and-hold circuits.

Abstract: A time-interleaved circuit includes an input buffer, a plurality of track-and-hold circuits, and a plurality of isolation inductors. The input buffer is configured to receive an input signal having an input voltage and to output an output signal having an output voltage. The track-and-hold circuits are electrically coupled in parallel with each other. Each track-and-hold circuit is electrically coupled in series with the input buffer. Each isolation inductor is electrically coupled to the output of the input buffer and at least one of the track-and-hold circuits.

Abstract: A piecewise linear gain amplifier circuit includes a differential preamplifier and a plurality of transconductors. The differential preamplifier is electrically coupled to a differential input having an input voltage. The transconductors are electrically coupled in parallel with each other. Each transconductor includes a respective differential input that is electrically coupled to a differential output of the differential preamplifier. In addition, each transconductor includes a respective differential output that is electrically coupled to a common differential PWL output. Each transconductor has a different linear input range. An optional attenuation circuit can be electrically coupled in parallel to the differential preamplifier. The differential output of the attenuation circuit can be electrically coupled to a differential input of another transconductor, and that transconductor can have a differential output that is electrically coupled to the common differential PWL output.

Abstract: A time-interleaved circuit includes an input buffer, a plurality of track-and-hold circuits, and a plurality of isolation inductors. The input buffer is configured to receive an input signal having an input voltage and to output an output signal having an output voltage. The track-and-hold circuits are electrically coupled in parallel with each other. Each track-and-hold circuit is electrically coupled in series with the input buffer. Each isolation inductor is electrically coupled to the output of the input buffer and at least one of the track-and-hold circuits.

Abstract: An amplifier circuit. In some embodiments, the amplifier circuit includes: a telescopic amplifier, and a common mode feedback amplifier. The telescopic amplifier has a first signal input, a second signal input, a first output, a second output, a common mode feedback input, a first pole-splitting capacitor, and a second pole-splitting capacitor. The common mode feedback amplifier has an output connected to the common mode feedback input of the telescopic amplifier. The first pole-splitting capacitor is connected between the common mode feedback input of the telescopic amplifier and the first output of the telescopic amplifier, and the second pole-splitting capacitor is connected between the common mode feedback input of the telescopic amplifier and the second output of the telescopic amplifier.

Abstract: A clock driver circuit. In some embodiments the clock driver circuit includes an output stage, a first voltage source, and an output impedance adjusting circuit. The output stage includes a first transistor connected to the first voltage source and to an output of the drive circuit. The drive circuit is configured to operate in one of, at least, a first state, and a second state. The output impedance adjusting circuit is configured to reduce a difference between an output impedance of the drive circuit in: the first state, in which the first transistor is turned on and the first voltage source is at a first supply voltage, and the second state, in which the first transistor is turned on and the first voltage source is at a second supply voltage different from the first supply voltage.

Abstract: A single-pole double-throw switch. In some embodiments, the switch includes a first switching transistor connected between a common terminal of the single-pole double-throw switch and a first switched terminal of the single-pole double-throw switch, a second switching transistor connected between the common terminal of the single-pole double-throw switch and a second switched terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the first switching transistor, and a second auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the second switching transistor.

Abstract: An amplifier circuit. In some embodiments, the amplifier circuit includes: a telescopic amplifier, and a common mode feedback amplifier. The telescopic amplifier has a first signal input, a second signal input, a first output, a second output, a common mode feedback input, a first pole-splitting capacitor, and a second pole-splitting capacitor. The common mode feedback amplifier has an output connected to the common mode feedback input of the telescopic amplifier. The first pole-splitting capacitor is connected between the common mode feedback input of the telescopic amplifier and the first output of the telescopic amplifier, and the second pole-splitting capacitor is connected between the common mode feedback input of the telescopic amplifier and the second output of the telescopic amplifier.

Abstract: In one embodiment, techniques herein determine a plurality of resources loaded during rendering of a web page on a client device, and determine a duration of time taken for each of the plurality of resources to fully load. Accordingly, the techniques herein may then cluster the plurality of resources into clusters, comprising a first cluster consisting of resources having the shortest durations of the plurality of resources and a second cluster consisting of resources having the longest durations of the plurality of resources. Those resources of the first cluster may then be classified as cached resources, while those resources of the second cluster may be classified as non-cached resources.

Abstract: An amplifier circuit. In some embodiments, the amplifier circuit includes: a telescopic amplifier, and a common mode feedback amplifier. The telescopic amplifier has a first signal input, a second signal input, a first output, a second output, a common mode feedback input, a first pole-splitting capacitor, and a second pole-splitting capacitor. The common mode feedback amplifier has an output connected to the common mode feedback input of the telescopic amplifier. The first pole-splitting capacitor is connected between the common mode feedback input of the telescopic amplifier and the first output of the telescopic amplifier, and the second pole-splitting capacitor is connected between the common mode feedback input of the telescopic amplifier and the second output of the telescopic amplifier.

Abstract: A clock driver circuit. In some embodiments the clock driver circuit includes an output stage, a first voltage source, and an output impedance adjusting circuit. The output stage includes a first transistor connected to the first voltage source and to an output of the drive circuit. The drive circuit is configured to operate in one of, at least, a first state, and a second state. The output impedance adjusting circuit is configured to reduce a difference between an output impedance of the drive circuit in: the first state, in which the first transistor is turned on and the first voltage source is at a first supply voltage, and the second state, in which the first transistor is turned on and the first voltage source is at a second supply voltage different from the first supply voltage.

Abstract: A single-pole double-throw switch. In some embodiments, the switch includes a first switching transistor connected between a common terminal of the single-pole double-throw switch and a first switched terminal of the single-pole double-throw switch, a second switching transistor connected between the common terminal of the single-pole double-throw switch and a second switched terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the first switching transistor, and a second auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the second switching transistor.

Abstract: A clock driver circuit. In some embodiments the clock driver circuit includes an output stage, a first voltage source, and an output impedance adjusting circuit. The output stage includes a first transistor connected to the first voltage source and to an output of the drive circuit. The drive circuit is configured to operate in one of, at least, a first state, and a second state. The output impedance adjusting circuit is configured to reduce a difference between an output impedance of the drive circuit in: the first state, in which the first transistor is turned on and the first voltage source is at a first supply voltage, and the second state, in which the first transistor is turned on and the first voltage source is at a second supply voltage different from the first supply voltage.

Abstract: In one embodiment, techniques herein determine a plurality of resources loaded during rendering of a web page on a client device, and determine a duration of time taken for each of the plurality of resources to fully load. Accordingly, the techniques herein may then cluster the plurality of resources into clusters, comprising a first cluster consisting of resources having the shortest durations of the plurality of resources and a second cluster consisting of resources having the longest durations of the plurality of resources. Those resources of the first cluster may then be classified as cached resources, while those resources of the second cluster may be classified as non-cached resources.

Abstract: A single-pole double-throw switch. In some embodiments, the switch includes a first switching transistor connected between a common terminal of the single-pole double-throw switch and a first switched terminal of the single-pole double-throw switch, a second switching transistor connected between the common terminal of the single-pole double-throw switch and a second switched terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the first switching transistor, and a second auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the second switching transistor.

Abstract: An amplifier circuit. In some embodiments, the amplifier circuit includes: a telescopic amplifier, and a common mode feedback amplifier. The telescopic amplifier has a first signal input, a second signal input, a first output, a second output, a common mode feedback input, a first pole-splitting capacitor, and a second pole-splitting capacitor. The common mode feedback amplifier has an output connected to the common mode feedback input of the telescopic amplifier. The first pole-splitting capacitor is connected between the common mode feedback input of the telescopic amplifier and the first output of the telescopic amplifier, and the second pole-splitting capacitor is connected between the common mode feedback input of the telescopic amplifier and the second output of the telescopic amplifier.

Abstract: Traditionally, latched comparators have suffered from performance problems related to exposure of the latch to load capacitances. Even attempts to isolate the latch from the load capacitances by way of resistors has resulted in performance problems (namely, voltage swing degradation). Here, however, a latched comparator is provided that employs inductors to generally provide isolation from load capacitances, which generally improves performance. Moreover, the latch has been modified to accommodate the inductors during a track period (namely, provision of grounding paths).

Abstract: Traditionally, latched comparators have suffered from performance problems related to exposure of the latch to load capacitances. Even attempts to isolate the latch from the load capacitances by way of resistors has resulted in performance problems (namely, voltage swing degradation). Here, however, a latched comparator is provided that employs inductors to generally provide isolation from load capacitances, which generally improves performance. Moreover, the latch has been modified to accommodate the inductors during a track period (namely, provision of grounding paths).