Abstract: Apparatuses, systems, and techniques for supporting fairness of multiple context sharing cryptographic hardware. An accelerator circuit includes a copy engine (CE) with AES-GCM hardware configured to perform both encryption and authentication of data transfers for multiple applications or multiple data streams in a single application or belonging to a single user. The CE splits a data transfer of a specified size into a set of partial transfers. The CE sequentially executes the set of partial transfers using a context for a period of time (e.g., a timeslice) for an application. The CE stores in a secure memory for the application one or more data for encryption or decryption (e.g., a hash key, a block counter, etc.) computed from a last partial transfer. The one or more data for encryption or decryption are retrieved and used when data transfers for the application is resumed by the CE.

Abstract: Apparatuses, systems, and techniques for supporting fairness of multiple context sharing cryptographic hardware. An accelerator circuit includes a copy engine (CE) with AES-GCM hardware configured to perform both encryption and authentication of data transfers for multiple applications or multiple data streams in a single application or belonging to a single user. The CE splits a data transfer of a specified size into a set of partial transfers. The CE sequentially executes the set of partial transfers using a context for a period of time (e.g., a timeslice) for an application. The CE stores in a secure memory for the application one or more data for encryption or decryption (e.g., a hash key, a block counter, etc.) computed from a last partial transfer. The one or more data for encryption or decryption are retrieved and used when data transfers for the application is resumed by the CE.

Abstract: Apparatuses, systems, and techniques for handling faults by a direct memory access (DMA) engine. When a DMA engine detects an error associated with an encryption or decryption operation, the DMA engine reports the error to a CPU, which may be executing an untrusted software directing a DMA operation, and the secure processor. The DMA engine waits for clearance from the secure processor before responding to further directions from the potentially untrusted software.

Abstract: Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.

Abstract: The subject application relates to computing an authentication tag for partial transfers scheduled across multiple direct memory access (DMA) engines. Apparatuses, systems, and techniques are described for computing an authentication tag for a data transfer when the data transfer is scheduled as partial transfers across a specified number of direct memory access (DMA) engines. An orchestration circuit stores partial authentication tags, computed by the DMA engines, and corresponding adjustment exponents during one or more rounds in which the partial transfers are scheduled and processed by the specified number of DMA engines. During a last round, a combined authentication tag can be computed based on the partial authentication tags and the corresponding adjustment exponents stored by the orchestration circuit during the rounds.

Abstract: Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.

Abstract: A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to a first processing module and a second processing module. The first processing module has a priority higher than a priority of the second processing module. The dispatch module includes a workload counter associated with the first processing module to provide an indication of a workload at the first processing module. The dispatch module initiates a clock signal at the second processing module only if the indication of the workload at the first processing module satisfies a criterion. The dispatch module sends a data unit to the second processing module for processing only if the indication of the workload at the first processing module satisfies a criterion.

Abstract: Described herein are a method and a system for extracting issues based on ticket mining. In one implementation, a plurality of tickets comprising descriptions of the issues in computing systems are received. The received descriptions are then cleaned by removing unwanted details. Upon cleaning, the clean descriptions are mapped with descriptions stored in service catalog data to obtain unmapped clean descriptions. In an example, the unmapped clean descriptions include one of user-generated descriptions, system-generated descriptions, and both the user-generated descriptions and the system-generated descriptions. For the user-generated descriptions; the issues are extracted by pre-processing the user-generated descriptions, determining keywords from the processed unmapped clean descriptions, constructing n-grams of keywords from the extracted keywords, and extracting the n-grams of keywords as the issues present in the computing systems.

Abstract: A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to a first processing module and a second processing module. The first processing module has a priority higher than a priority of the second processing module. The dispatch module includes a workload counter associated with the first processing module to provide an indication of a workload at the first processing module. The dispatch module initiates a clock signal at the second processing module only if the indication of the workload at the first processing module satisfies a criterion. The dispatch module sends a data unit to the second processing module for processing only if the indication of the workload at the first processing module satisfies a criterion.

Abstract: A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to multiple processing modules, each having a first clock configuration and a second clock configuration. The dispatch module, at a first time, changes a first processing module included in the multiple processing modules from a first clock configuration to a second clock configuration. The dispatch module prohibits, at a second time within a predetermined time period and after the first time, a second processing module included in the multiple processing modules from changing from the first clock configuration to the second clock configuration if an indicator associated with a number of changes of the multiple processing modules between a first clock configuration and a second clock configuration within the predetermined time period and prior to the second time satisfies a criterion.

Abstract: A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to multiple processing modules, each having a first clock configuration and a second clock configuration. The dispatch module, at a first time, changes a first processing module included in the multiple processing modules from a first clock configuration to a second clock configuration. The dispatch module prohibits, at a second time within a predetermined time period and after the first time, a second processing module included in the multiple processing modules from changing from the first clock configuration to the second clock configuration if an indicator associated with a number of changes of the multiple processing modules between a first clock configuration and a second clock configuration within the predetermined time period and prior to the second time satisfies a criterion.

Abstract: Described herein are a method and a system for extracting issues based on ticket mining. In one implementation, a plurality of tickets comprising descriptions of the issues in computing systems are received. The received descriptions are then cleaned by removing unwanted details. Upon cleaning, the clean descriptions are mapped with descriptions stored in service catalog data to obtain unmapped clean descriptions. In an example, the unmapped clean descriptions include one of user-generated descriptions, system-generated descriptions, and both the user-generated descriptions and the system-generated descriptions. For the user-generated descriptions; the issues are extracted by pre-processing the user-generated descriptions, determining keywords from the processed unmapped clean descriptions, constructing n-grams of keywords from the extracted keywords, and extracting the n-grams of keywords as the issues present in the computing systems.

Abstract: A method of providing a programmer with a visualization of power usage. The method is especially suitable for integration within a debugging process (FIG. 20). A windows-type display (160, 170, 180, 190) displays sections of computer code (160a, 170a), as well as numerical values representing power usage (160b, 170b). Next to each section of code, some sort of visual representation of power usage is displayed, such as a bar of a bar graph (160c, 170c). Alternatively, the code can be highlighted if power usage exceeds a given threshold, or comments can be provided next to the code for optimizing power usage.