Abstract: A computer system, a printed circuit board assembly, and a multiple die semiconductor assembly are provided comprising first and second semiconductor dies and an intermediate substrate. The first semiconductor die defines a first active surface including at least one conductive bond pad. The second semiconductor die defines a second active surface including at least one conductive bond pad. The intermediate substrate is positioned between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die such that a first surface of the intermediate substrate faces the first active surface and such that a second surface of the intermediate substrate faces the second active surface. The first semiconductor die is electrically coupled to the intermediate substrate by at least one topographic contact extending from the first active surface to the first surface of the intermediate substrate.

Abstract: A multichip semiconductor assembly comprising a semiconductor chip stack comprising first and second chips, each having an active surface including an integrated circuit and a plurality of input/output contact pads; a leadframe for interconnecting semiconductor integrated circuits having a plurality of leads, portions of said leads comprising undulating patterns and a surface metallurgy for promoting solder wetting, said leadframe being disposed between said first and second chips, and said active surface of said first chip positioned in front of said active surface of said second chip; and connections between each of said contact pads of said first chip to one of said leads, respectively, and between each of said contact pads of said second chip to one of said leads, respectively, said connections comprising solder balls, whereby the connections to at least one of said leads are common between said first and second chips.

Abstract: A stacked multichip assemblage including a plurality of integrated circuit die directly attached to a substrate having pads corresponding to terminals on the die, and interconnections between the die, and also to external contacts. The stacked integrated circuit arrangement includes a first chip(s) having an array of bumped terminals positioned on the corresponding pads of the substrate, a larger integrated circuit chip having perimeter bump terminals located over the first chip, and the terminals directly bonded to corresponding pads on the substrate.

Abstract: Multichip semiconductor assembly comprising a semiconductor chip stack comprising first and second chips, each having an active surface including an integrated circuit and a plurality of input/output contact pads, and a passive surface; a leadframe for interconnecting semiconductor integrated circuits having first and second surfaces, a plurality of leads, and a chip mount pad, said leadframe being disposed between said first and second chips, and at least a portion of said passive surface of said first chip being attached to said first surface of said chip mount pad; bonding wire connections between each of said contact pads of said first chip to said first surface of one of said leads, respectively; and solder ball connections between each of said contact pads of said second chip to said second surface of one of said leads, respectively, whereby the connections to at least one of said leads are common between said first and second chips.