Patents by Inventor Vajram GHANTASALA

Vajram GHANTASALA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FINE GRAIN POWER GATING
    Publication number: 20240322819
    Abstract: Aspects of the present disclosure provide cells including integrated switches and/or integrated clamps. In some aspects, a cell includes a circuit having an input and an output, and a switch coupled between a supply rail and the circuit, wherein the switch is configured to receive an enable signal, turn on when the enable signal has a first logic value, and turn off when the enable signal has a second logic value. The cell also includes a first clamp coupled to the output of the circuit, wherein the first clamp is configured to clamp the output of the circuit when the enable signal has the second logic value.
    Type: Application
    Filed: March 23, 2023
    Publication date: September 26, 2024
    Inventors: Giby SAMSON, Ramaprasath VILANGUDIPITCHAI, Pavan Kumar PATIBANDA, Joshua ONG, Chethan SWAMYNATHAN, Vajram GHANTASALA, Venugopal BOYNAPALLI, Madan KRISHNAPPA, Vineet OORAMKUMARATH, Mohamed Saud MUSLIYARAKATH
  • Mitigation of duty-cycle distortion
    Patent number: 11881862
    Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: January 23, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Udayakiran Kumar Yallamaraju, Xia Li, Pankaj Deshmukh, Vajram Ghantasala, Bin Yang, Vishal Mishra, Bharatheesha Sudarshan Jagirdar, Arun Sundaresan Iyer, Amod Phadke, Vanamali Bhat
  • MITIGATION OF DUTY-CYCLE DISTORTION
    Publication number: 20230058318
    Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.
    Type: Application
    Filed: August 17, 2021
    Publication date: February 23, 2023
    Inventors: Udayakiran Kumar YALLAMARAJU, Xia LI, Pankaj DESHMUKH, Vajram GHANTASALA, Bin YANG, Vishal MISHRA, Bharatheesha Sudarshan JAGIRDAR, Arun Sundaresan IYER, Amod PHADKE, Vanamali BHAT