Abstract: A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.

Abstract: A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.

Abstract: A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.

Abstract: According to some embodiments, a dynamic region in a register file may be defined for an operand. The defined region may, for example, store multiple data elements, each data element being associated with an execution channel of an execution engine. Information may then be stored into and/or retrieved from the register file in accordance with the defined region.

Abstract: A machine readable storage media containing executable program instructions which when executed cause a digital processing system to set a plurality of operands and operators. A plurality of texture maps are sent to a processor for texture compositing. Operands are selected for a texture operation. A first logic is used wherein if the circulation of blend stages is equal to a number of blend stages, then a color saturation is performed, and a second logic that if the circulation number of blend stages does not equal the number of blend stages then at least one operand is selected for another texture compositing operation.

Abstract: According to some embodiments, a dynamic region in a register file may be described for an operand. The described region may, for example, store multiple data elements, each data element being associated with an execution channel of an execution engine. Information may then be stored into and/or retrieved from the register file in accordance with the described region.

Abstract: A configurable filter module for providing shared filter resource between an overlay engine and a texture mapping engine of a graphics system. The configurable filter may comprise a plurality of linear blend units each of which receives data input from one of the overlay engine and a mapping engine cache, and generates a linear blend filter output respectively; and a filter output multiplexer which receives data output from the linear blend units and selects a proper byte ordering output, wherein the linear blend units serve as an overlay interpolator filter to perform linear blending of the data input from the overlay engine during a linear blend mode, and serve as a texture bilinear filter to perform bilinear filtering of the data input from the mapping engine cache during a bilinear filtering mode.

Abstract: According to some embodiments, a value is retrieved from a location in an index register. A region in a register file may then be determined based at least in part on the value. Information may then be stored into the determined region of the register file.

Abstract: A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.

Abstract: According to some embodiments, a dynamic region in a register file may be described for an operand. The described region may, for example, store multiple data elements, each data element being associated with an execution channel of an execution engine. Information may then be stored into and/or retrieved from the register file in accordance with the described region.

Abstract: A texture data reading apparatus includes a cache memory including a plurality of read ports and a plurality of regions to store pixel texture data. An address comparator includes a plurality of input ports to receive incoming pixels, wherein the address comparator compares the memory addresses associated with the incoming pixels to determine which regions of cache memory are accessed. A cache lookup device accesses new texture data from the cache memory for the incoming pixels in the same clock cycle in response to the number of memory regions accessed being less than or equal to the number of cache memory read ports.

Abstract: An anisotropic filtering technique includes defining pixel elements in two dimensions and defining at least one object having three dimensional surfaces in a three-dimensional model space and storing texel elements in two dimensions defining a texture map bearing a relationship to the three dimensional surfaces of the at least one object. Each pixel element to be texture mapped is divided into a group of sub-pixel elements and the sub-pixel elements are separately texture mapped. The resultant textures of the sub-pixel elements are averaged to obtain a texture for their respective pixel element.

Abstract: A method and circuit are provided for color space conversion of Y (luminance) and UV (chrominance) components from a planar YUV 4:2:0 format to an interleaved, or packed YUV 4:2:2 format, and from an interleaved, or packed YUV 4:2:2 format to a planar YUV 4:2:0 format. The method for both conversions includes reading source data, interpolating the sampled YUV component values, and performing a pass to thereby write the converted YUV component values in three passes, one pass for all values of the respective YUV components.

Abstract: A method and circuit are provided for color space conversion of Y (luminance) and UV (chrominance) components from a planar YUV 4:2:0 format to an interleaved, or packed YUV 4:2:2 format, and from an interleaved, or packed YUV 4:2:2 format to a planar YUV 4:2:0 format. The method for both conversions includes reading source data, interpolating the sampled YUV component values, and performing a pass to thereby write the converted YUV component values in three passes, one pass for all values of the respective YUV components.