Patents by Inventor Val Gont
Val Gont has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7873203Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.Type: GrantFiled: August 29, 2008Date of Patent: January 18, 2011Assignee: Semiconductor Insights Inc.Inventors: Vyacheslav L. Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg
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Patent number: 7643665Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.Type: GrantFiled: August 31, 2004Date of Patent: January 5, 2010Assignee: Semiconductor Insights Inc.Inventors: Vyacheslav L. Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg
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Patent number: 7580557Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.Type: GrantFiled: August 29, 2008Date of Patent: August 25, 2009Assignee: Semiconductor Insights Inc.Inventors: Vyacheslav L. Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg
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Publication number: 20080317327Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.Type: ApplicationFiled: August 29, 2008Publication date: December 25, 2008Inventors: Vyacheslav L. Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg
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Publication number: 20080317328Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.Type: ApplicationFiled: August 29, 2008Publication date: December 25, 2008Inventors: Vyacheslav L. Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg
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Publication number: 20070256037Abstract: The present invention provides an accurate and efficient method of organizing circuitry from a net-list of an integrated circuit, by the steps of generating a reference pattern; identifying the potential matches in the net-list using inexact graph matching; further analyzing the matches to determine if they match the reference pattern; and organizing the net-list into a hierarchy by replacing the identified instances with higher-level representations.Type: ApplicationFiled: April 26, 2006Publication date: November 1, 2007Inventors: Vyacheslav Zavadsky, Edward Keyes, Sergei Sourjko, Val Gont, Stephen Begg, Jason Abt
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Patent number: 7278121Abstract: The method and apparatus in accordance with the present invention reduces the data size of a layout data structure by reducing the amount of electrically redundant interconnects within a bank of interconnects. Electrically redundant interconnects are the repetitive interconnects within a bank of interconnects which do not contribute to the understanding of the IC. Therefore, a number of these interconnects may be deleted from the banks in the layout data structure, provided that enough interconnects remain to maintain the electrical connectivity and the visual representation of the bank.Type: GrantFiled: August 23, 2004Date of Patent: October 2, 2007Assignee: Semiconductor Insights Inc.Inventors: Elmehdi Aitnouri, Edward Keyes, Stephen Begg, Val Gont, Dale McIntyre, Mohammed Ouali, Vyacheslav Zavadsky
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Patent number: 7207018Abstract: The method and apparatus in accordance with the present invention determines the locations of incorrectly connected polygons in a polygon representation of an integrated circuit layout. These incorrectly connected polygons result in short circuits, which often occur for major signal busses such as power and ground. It can be time-consuming to determine the exact location of the short. The invention includes the step of tessellating the polygon representation, including each conductive layer, into predetermined shapes such as triangles or trapezoids. Each of the triangles or trapezoids is then translated into a node for the development of a nodal network where nodes are connected directly to one another to represent shapes having edges adjacent to other shape edges. The current capacity of each connection between adjacent nodes is then specified. Two nodes that are electrically connected to the incorrectly connected polygons are selected and used as parameters for a network flow analysis algorithm.Type: GrantFiled: August 4, 2004Date of Patent: April 17, 2007Assignee: Semiconductor Insights Inc.Inventors: Vyacheslav L. Zavadsky, Elmehdi Aitnouri, Edward Keyes, Jason Abt, Val Gont, Stephen Begg
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Patent number: 7013028Abstract: An editor in a computer system for editing an schematic having a number of pages. The editor may cut a selected portion of the schematic from any one of the schematic pages, paste the cut portion of the schematic onto any one of the schematic pages, and connect nets located on the same schematic page. The editor may search for objects such as signal labels and cells within the schematic netlist as well as other editing functions. Further a navigator is provided for interactively viewing netlist data from a high level schematic where the data includes schematic page numbers, cell names, nets, signal labels and segments. The project viewer software and project schematic netlist data may be contained in a computer-readable medium. The project viewer software controls output schematic images and enables a user to view, trace and search objects throughout the project netlist data.Type: GrantFiled: August 3, 2001Date of Patent: March 14, 2006Assignee: Semiconductor Insights Inc.Inventors: Val Gont, Jason Abt, Larry Lam
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Publication number: 20060045325Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.Type: ApplicationFiled: August 31, 2004Publication date: March 2, 2006Inventors: Vyacheslav Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg
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Publication number: 20060041849Abstract: The method and apparatus in accordance with the present invention reduces the data size of a layout data structure by reducing the amount of electrically redundant interconnects within a bank of interconnects. Electrically redundant interconnects are the repetitive interconnects within a bank of interconnects which do not contribute to the understanding of the IC. Therefore, a number of these interconnects may be deleted from the banks in the layout data structure, provided that enough interconnects remain to maintain the electrical connectivity and the visual representation of the bank.Type: ApplicationFiled: August 23, 2004Publication date: February 23, 2006Applicant: Semiconductor Insights Inc.Inventors: Elmehdi Aitnouri, Edward Keyes, Stephen Begg, Val Gont, Dale Mclntyre, Mohammed Ouali, Vyacheslav Zavadsky
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Publication number: 20060031792Abstract: The method and apparatus in accordance with the present invention determines the locations of incorrectly connected polygons in a polygon representation of an integrated circuit layout. These incorrectly connected polygons result in short circuits, which often occur for major signal busses such as power and ground. It can be time-consuming to determine the exact location of the short. The invention includes the step of tessellating the polygon representation, including each conductive layer, into predetermined shapes such as triangles or trapezoids. Each of the triangles or trapezoids is then translated into a node for the development of a nodal network where nodes are connected directly to one another to represent shapes having edges adjacent to other shape edges. The current capacity of each connection between adjacent nodes is then specified. Two nodes that are electrically connected to the incorrectly connected polygons are selected and used as parameters for a network flow analysis algorithm.Type: ApplicationFiled: August 4, 2004Publication date: February 9, 2006Applicant: Semiconductor Insights Inc.Inventors: Vyacheslav Zavadsky, Elmehdi Aitnouri, Edward Keyes, Jason Abt, Val Gont, Stephen Begg
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Patent number: 6738957Abstract: A process in a computer system for generating a high level schematic from a project schematic of basic components which comprises scanning the project schematic for a predetermined cell, wherein the cell is made up of a select group of components and their interconnections, and replacing the select group of components on every occurrence that it is found in the project schematic by a cell symbol having input and outputs to generate the high level schematic. The process may also be repeated for other predetermined cells which may be selected from a library or created by the user.Type: GrantFiled: August 3, 2001Date of Patent: May 18, 2004Assignee: Semiconductor Insights Inc.Inventors: Val Gont, Jason Abt, Larry Lam, Alexei Ioudovski
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Publication number: 20020023107Abstract: A process in a computer system for generating a high level schematic from a project schematic of basic components which comprises scanning the project schematic for a predetermined cell, wherein the cell is made up of a select group of components and their interconnections, and replacing the select group of components on every occurrence that it is found in the project schematic by a cell symbol having input and outputs to generate the high level schematic. The process may also be repeated for other predetermined cells which may be selected from a library or created by the user.Type: ApplicationFiled: August 3, 2001Publication date: February 21, 2002Applicant: Semiconductor Insights Inc.Inventors: Val Gont, Jason Abt, Larry Lam, Alexei Ioudovski
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Publication number: 20020018583Abstract: An editor in a computer system for editing an schematic having a number of pages. The editor may cut a selected portion of the schematic from any one of the schematic pages, paste the cut portion of the schematic onto any one of the schematic pages, and connect nets located on the same schematic page. The editor may search for objects such as signal labels and cells within the schematic netlist as well as other editing functions. Further a navigator is provided for interactively viewing netlist data from a high level schematic where the data includes schematic page numbers, cell names, nets, signal labels and segments. The project viewer software and project schematic netlist data may be contained in a computer-readable medium. The project viewer software controls output schematic images and enables a user to view, trace and search objects throughout the project netlist data.Type: ApplicationFiled: August 3, 2001Publication date: February 14, 2002Applicant: Semiconductor Insights Inc.Inventors: Val Gont, Jason Abt, Larry Lam