Patents by Inventor Val Pevzner

Val Pevzner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for efficient FPGA packing
    Patent number: 9147025
    Abstract: A method for programming a cluster-based field programmable gate array (FPGA) device includes providing a netlist and cluster size information, translating the netlist into a hypergraph, partitioning the hypergraph into multiple partitions and optimizing the Rent characteristic, translating the partitions into clusters, placing the clusters on the FPGA device, routing interconnects using a pre-fabricated routing resource on the FPGA device, generating a programming bitstream in response to the placing and routing, and providing the programming bitstream to the FPGA device to realize the user design.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: September 29, 2015
    Assignee: Microsemi SoC Corporation
    Inventors: Wenyi Feng, Jonathan Greene, Kristofer Vorwerk, Val Pevzner, Arunangshu Kundu
  • Method for Efficient FPGA Packing
    Publication number: 20150020038
    Abstract: A method for programming a cluster-based field programmable gate array (FPGA) device includes providing a netlist and cluster size information, translating the netlist into a hypergraph, partitioning the hypergraph into multiple partitions and optimizing the Rent characteristic, translating the partitions into clusters, placing the clusters on the FPGA device, routing interconnects using a pre-fabricated routing resource on the FPGA device, generating a programming bitstream in response to the placing and routing, and providing the programming bitstream to the FPGA device to realize the user design.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 15, 2015
    Inventors: Wenyi Feng, Jonathan Greene, Kristofer Vorwerk, Val Pevzner, Arunangshu Kundu