Abstract: The invention relates to a computer architecture and functional architecture for the operation of electric power steering, to an electronic control unit, and to power steering, having a first group of modules with a high probability of failure and a second group of modules with a low probability of failure. In this case, the modules of the first group have a higher probability of failure than the modules of the second group. The first group of modules is maintained redundantly in this case and, as a result, divided into main modules and into the redundant implementation of what are known as secondary modules. The main modules are arranged on a main control path and the secondary modules are respectively arranged on a secondary control path. Each of these control paths ultimately produces a control signal, i.e., a main control signal and a secondary control signal. A multiplexer is used to decide which of these two control signals is forwarded to modules from the second group.

Abstract: The invention relates to a computer architecture and functional architecture for the operation of electric power steering, to an electronic control unit, and to power steering, having a first group of modules with a high probability of failure and a second group of modules with a low probability of failure. In this case, the modules of the first group have a higher probability of failure than the modules of the second group. The first group of modules is maintained redundantly in this case and, as a result, divided into main modules and into the redundant implementation of what are known as secondary modules. The main modules are arranged on a main control path and the secondary modules are respectively arranged on a secondary control path. Each of these control paths ultimately produces a control signal, i.e., a main control signal and a secondary control signal. A multiplexer is used to decide which of these two control signals is forwarded to modules from the second group.

Abstract: An electronic device having a pin for setting its mode of operation, wherein the pin is connected or connectable to a first connection of a resistor, wherein the electronic device is arranged to detect a location of the resistor, wherein the electronic device is arranged to detect a size of the resistor, wherein the electronic device is arranged to determine a first setting based on the location of the resistor, and wherein the electronic device is arranged to determine a second setting based on the size of the resistor.

Abstract: An integrated circuit device comprises a first integrated circuit and a second integrated circuit wherein the first and second integrated circuits are comprised on a single semiconductor die. The second integrated circuit is a safety circuit arranged to monitor the operation of the first integrated circuit, report any detected faults and drive the device into a failsafe state if a fault is detected. The first integrated circuit may be a power management module for a safety critical system. An isolation barrier in the form of a trench is formed between the two integrated circuits so that the safety circuit is protected from any high voltage or thermal stresses arising in the first integrated circuit. The device has particular application to automotive safety-critical systems such as electric power steering systems.

Abstract: A power safety circuit comprises a power sense terminal; an output terminal; an output driver unit connected to the output terminal; an input terminal connectable to receive a first power from a power source and arranged to supply the first power to the output driver unit; and a power detection unit arranged to detect a state of the input terminal and provide a power sense signal to the power sense terminal; wherein the power sense terminal is arranged to supply a second power to the output driver unit when the power sense signal indicates a level of the first power below a minimum level for driving the output terminal. An integrated circuit device comprises at least one power safety circuit. A safety critical system comprises at least one integrated circuit device with at least one power safety circuit.

Abstract: An electronic device for generating an error signal in response to an electrostatic discharge perturbation is described. The device may comprise: a detection unit for generating a detection signal in response to said electrostatic discharge perturbation, said detection signal correlating in time with said electrostatic discharge perturbation; a clock for generating a clock signal having a clock period; and a protection unit for generating an error signal in response to said detection signal only when a duration of said detection signal exceeds a predefined multiple of said clock period. A method of generating an error signal in response to an electrostatic discharge perturbation, for protecting electronic circuitry, is also disclosed.

Abstract: A voltage regulator circuit arranged to receive a voltage supply signal, and to output a regulated voltage signal is described. The voltage regulator circuit comprises at least one switched mode power supply component selectively configurable to perform regulation of the voltage supply signal, at least one linear voltage regulator component selectively configurable to perform regulation of the voltage supply signal, and at least one controller component.

Abstract: A DC to DC converter including a buck converter, a boost converter, and a control unit, wherein the control unit is arranged to calculate an error voltage of the buck converter Verr_buck based on a feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the buck converter Vref_buck, and wherein the control unit is arranged to calculate an error voltage of the boost converter Verr_boost based on the feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the boost converter Vref_boost, wherein the reference voltage of the boost converter Vref_boost is shifted by an offset Voffset as compared to the reference voltage of the buck converter Vref_buck.

Abstract: A packaged semiconductor device comprising a package and a semiconductor device is described. The semiconductor device comprises a first and a second GND-pad bonded to one or more GND-pins with a first and a second bond wire respectively, a first functional pad bonded to a first functional pin with a third bond wire, a semiconductor layer of a P-type conductivity, a first semiconductor component and a second semiconductor component. The first semiconductor component is arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current to the first GND-pad from the first P-region to the first GND-pad via at least a first PN-junction. The second semiconductor component comprises a second N-type region of a terminal of the second semiconductor component associated with the first functional pad. The first GND-pad is in contact with a second P-type region. The second GND-pad is in contact with a third N-type region.

Abstract: An integrated circuit device comprises a first integrated circuit and a second integrated circuit wherein the first and second integrated circuits are comprised on a single semiconductor die. The second integrated circuit is a safety circuit arranged to monitor the operation of the first integrated circuit, report any detected faults and drive the device into a failsafe state if a fault is detected. The first integrated circuit may be a power management module for a safety critical system. An isolation barrier in the form of a trench is formed between the two integrated circuits so that the safety circuit is protected from any high voltage or thermal stresses arising in the first integrated circuit. The device has particular application to automotive safety-critical systems such as electric power steering systems.

Abstract: A voltage regulator circuit arranged to receive a voltage supply signal, and to output a regulated voltage signal is described. The voltage regulator circuit comprises at least one switched mode power supply component selectively configurable to perform regulation of the voltage supply signal, at least one linear voltage regulator component selectively configurable to perform regulation of the voltage supply signal, and at least one controller component.

Abstract: A packaged semiconductor device comprising a package and a semiconductor device is described. The semiconductor device comprises a first and a second GND-pad bonded to one or more GND-pins with a first and a second bond wire respectively, a first functional pad bonded to a first functional pin with a third bond wire, a semiconductor layer of a P-type conductivity, a first semiconductor component and a second semiconductor component. The first semiconductor component is arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current to the first GND-pad from the first P-region to the first GND-pad via at least a first PN-junction. The second semiconductor component comprises a second N-type region of a terminal of the second semiconductor component associated with the first functional pad. The first GND-pad is in contact with a second P-type region. The second GND-pad is in contact with a third N-type region.

Abstract: An electronic device having a pin for setting its mode of operation, wherein the pin is connected or connectable to a first connection of a resistor, wherein the electronic device is arranged to detect a location of the resistor, wherein the electronic device is arranged to detect a size of the resistor, wherein the electronic device is arranged to determine a first setting based on the location of the resistor, and wherein the electronic device is arranged to determine a second setting based on the size of the resistor.

Abstract: An electronic device for generating an error signal in response to an electrostatic discharge perturbation is described. The device may comprise: a detection unit for generating a detection signal in response to said electrostatic discharge perturbation, said detection signal correlating in time with said electrostatic discharge perturbation; a clock for generating a clock signal having a clock period; and a protection unit for generating an error signal in response to said detection signal only when a duration of said detection signal exceeds a predefined multiple of said clock period. A method of generating an error signal in response to an electrostatic discharge perturbation, for protecting electronic circuitry, is also disclosed.

Abstract: A DC to DC converter including a buck converter, a boost converter, and a control unit, wherein the control unit is arranged to calculate an error voltage of the buck converter Verr_buck based on a feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the buck converter Vref_buck, and wherein the control unit is arranged to calculate an error voltage of the boost converter Verr_boost based on the feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the boost converter Vref_boost, wherein the reference voltage of the boost converter Vref_boost is shifted by an offset Voffset as compared to the reference voltage of the buck converter Vref_buck.

Abstract: A power safety circuit comprises a power sense terminal; an output terminal; an output driver unit connected to the output terminal; an input terminal connectable to receive a first power from a power source and arranged to supply the first power to the output driver unit; and a power detection unit arranged to detect a state of the input terminal and provide a power sense signal to the power sense terminal; wherein the power sense terminal is arranged to supply a second power to the output driver unit when the power sense signal indicates a level of the first power below a minimum level for driving the output terminal. An integrated circuit device comprises at least one power safety circuit. A safety critical system comprises at least one integrated circuit device with at least one power safety circuit.

Abstract: Method and apparatus for communicating on an electrical bus by generating a master logical signal on the electrical bus in the form of a pulse-width modulation signal. Generating a slave logical signal on the electrical bus in the form of a current signal. Reading the slave logical signal by sampling the magnitude of the current signal on the electrical bus, wherein magnitude of the current on the electrical bus is sampled at a point in the bit time when the voltage on the electrical bus has remained constant for a period longer than the shortest time that the voltage remains at any level during the bit time.

Abstract: A differential communication bus comprising a master module and a plurality of slave modules connected to at least first and second conductors whereby to communicate between the master and slave modules. The master module comprises a driver for applying first and second voltages respectively to the first and second conductors and for sourcing and sinking currents in the first and second conductors. The driver controls a difference between the first and second voltages and a common mode value of the first and second voltages. The driver includes first sourcing and sinking current limiters and second sourcing and sinking current limiters for limiting the currents in the first and second conductors. The master module is selectively responsive to a fault condition triggering simultaneous activation of the first and second sourcing current limiters or of the first and second sinking current limiters to disable the driver.

Abstract: A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.

Abstract: Method and apparatus for communicating on an electrical bus by generating a master logical signal on the electrical bus in the form of a pulse-width modulation signal. Generating a slave logical signal on the electrical bus in the form of a current signal. Reading the slave logical signal by sampling the magnitude of the current signal on the electrical bus, wherein magnitude of the current on the electrical bus is sampled at a point in the bit time when the voltage on the electrical bus has remained constant for a period longer than the shortest time that the voltage remains at any level during the bit time.