Abstract: A device for overcurrent protection, the device may include a main transistor that is configured to supply, via an output node, a load current to a load; a current limiting resistor; a replica transistor that is configured to provide a replica current to the current limiting resistor; wherein the replica current is smaller than the load current, wherein a value of the replica current is responsive to a value of the load current; an amplifier; a current limiting transistor; a variable signal source that is configured to output a reference signal; wherein a value of the reference signal is based on a main transistor voltage; wherein the amplifier is configured to prevent the load current from exceeding a first load current threshold by biasing the main transistor and the replica transistor with a bias signal; wherein a value of the bias signal is responsive to the reference signal and to the replica current.

Abstract: Some demonstrative embodiments include an apparatus including a low-voltage detector to detect whether a voltage difference between a first voltage of a first voltage domain and a second voltage of the first voltage domain is lower than a predefined voltage.

Abstract: Some demonstrative embodiments include an apparatus including a low-voltage detector to detect whether a voltage difference between a first voltage of a first voltage domain and a second voltage of the first voltage domain is lower than a predefined voltage.

Abstract: Some demonstrative embodiments include a level shifter to shift a high logic level and a low logic level of a Direct Current (DC) control signal of a first voltage domain to a high logic level and a low logic level of a second voltage domain, respectively.

Abstract: Some demonstrative embodiments include a level shifter to shift a high logic level and a low logic level of a Direct Current (DC) control signal of a first voltage domain to a high logic level and a low logic level of a second voltage domain, respectively.

Abstract: A device for overcurrent protection, the device may include a main transistor that is configured to supply, via an output node, a load current to a load; a current limiting resistor; a replica transistor that is configured to provide a replica current to the current limiting resistor; wherein the replica current is smaller than the load current, wherein a value of the replica current is responsive to a value of the load current; an amplifier; a current limiting transistor; a variable signal source that is configured to output a reference signal; wherein a value of the reference signal is based on a main transistor voltage; wherein the amplifier is configured to prevent the load current from exceeding a first load current threshold by biasing the main transistor and the replica transistor with a bias signal; wherein a value of the bias signal is responsive to the reference signal and to the replica current.

Abstract: A self-adjustable current source control circuit utilizes a replica output stage, a sink current source that generates a reference current, and a negative feedback circuit to generate a sink current between a linear regulator output terminal and ground only when a load circuit connected to the linear regulator is in a low power consuming state. The replica output stage includes an 1:N scaled replica of the linear regulator's NMOS (or NPN) output stage transistor, and the negative feedback circuit utilizes two PMOS (or PNP) negative feedback transistors having the same N:1 size ratio and connected as a common gate amplifier, whereby one of the two negative feedback transistors turns on to draw the desired sink current from the regulator output terminal only when the load current falls below N times the reference current (i.e., only the load current is drawn through the output stage transistor during high load current conditions).

Abstract: A self-adjustable current source control circuit utilizes a replica output stage, a sink current source that generates a reference current, and a negative feedback circuit to generate a sink current between a linear regulator output terminal and ground only when a load circuit connected to the linear regulator is in a low power consuming state. The replica output stage includes an 1:N scaled replica of the linear regulator's NMOS (or NPN) output stage transistor, and the negative feedback circuit utilizes two PMOS (or PNP) negative feedback transistors having the same N:1 size ratio and connected as a common gate amplifier, whereby one of the two negative feedback transistors turns on to draw the desired sink current from the regulator output terminal only when the load current falls below N times the reference current (i.e., only the load current is drawn through the output stage transistor during high load current conditions).

Abstract: A current limiting circuit for a linear regulator includes an output stage transistor and a replica transistor, which have gates coupled to receive an output voltage from a linear amplifier and sources coupled to load circuitry. A drain of the output stage transistor is coupled to a VDD supply terminal, while a drain of the replica transistor is coupled to the VDD supply terminal through a first resistor. The output stage transistor and replica transistor are operated in saturation, such that proportional currents flow through these transistors. The voltage drop across the first resistor provides a first voltage, which is applied to a second amplifier. A reference voltage is also applied to the second amplifier. When the first voltage becomes less than the reference voltage, a feedback transistor is enabled to pull down the output voltage of the linear amplifier, thereby limiting the output current supplied to the load circuitry.