Abstract: The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X) and a plurality of second sawing regions (301-311) running parallel to one another in a second direction (Y), having useful regions (10) which in each case contain an integrated circuit (100) and which are in each case arranged between respective adjacent first sawing regions (201-211) and respective adjacent second sawing regions (301-311), and at least one test structure region arranged in the first sawing regions (201-211) and the second sawing regions (301-311) with test structures formed therein for checking electrical parameters of semiconductor elements.

Abstract: A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an inner capacitor electrode of a trench capacitor by a dopant diffusion region with an interconnect is disclosed. Methods are disclosed for making an electrical measurement, to determine the nonreactive resistance of dopant diffusion regions, the so-called “buried straps”, without the measurement result being corrupted by the nonreactive resistance of a transistor channel. In accordance with one embodiment of the invention having a plurality of electrical connections of the capacitor electrode, static currents can also be conducted through a buried strap and the capacitor electrode. Embodiments are disclosed that make it possible to perform at novel test structures of a semiconductor wafer electrical resistance measurements, which cannot be carried out at memory cells of a memory cell array themselves.

Abstract: A test structure for determining the electrical properties of a memory cell in a matrix-like cell array constructed on the basis of the single-sided buried strap concept has a connection between internal electrodes in the storage capacitors in two adjacent memory cells in the direction of the row of active regions in order to produce a series circuit. A first selection transistor and a first storage capacitor in a first memory cell and a second selection transistor and a second storage capacitor in a second memory cell, the active regions of the first and second selection transistors not being connected between the first and second selection transistors via a contact-making bit line.

Abstract: A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an inner capacitor electrode of a trench capacitor by a dopant diffusion region with an interconnect is disclosed. Methods are disclosed for making an electrical measurement, to determine the nonreactive resistance of dopant diffusion regions, the so-called “buried straps”, without the measurement result being corrupted by the nonreactive resistance of a transistor channel. In accordance with one embodiment of the invention having a plurality of electrical connections of the capacitor electrode, static currents can also be conducted through a buried strap and the capacitor electrode. Embodiments are disclosed that make it possible to perform at novel test structures of a semiconductor wafer electrical resistance measurements, which cannot be carried out at memory cells of a memory cell array themselves.

Abstract: The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X) and a plurality of second sawing regions (301-311) running parallel to one another in a second direction (Y), having useful regions (10) which in each case contain an integrated circuit (100) and which are in each case arranged between respective adjacent first sawing regions (201-211) and respective adjacent second sawing regions (301-311), and at least one test structure region arranged in the first sawing regions (201-211) and the second sawing regions (301-311) with test structures formed therein for checking electrical parameters of semiconductor elements.

Abstract: A semiconductor disk which exhibits chip areas arranged next to one another and separated from one another by a kerf. The chip areas in each case exhibit a multiplicity of similar device patterns, such that at least one fill area with fill patterns is arranged in the kerf, and the fill patterns in the kerf and the device patterns in the chip areas are essentially similarly constructed.

Abstract: The invention proposes a semiconductor wafer with a test structure for detecting parasitic contact structures on the semiconductor wafer, in which a first interconnect plane (A) contains interconnects (1) running parallel to one another and a second interconnect (2) that is arranged between the latter. The two first interconnects (1) are connected by means of contact elements (4) arranged above them, to a third interconnect (3) that runs in a second interconnect plane (B) transverse to the first and second interconnects, and that also crosses the second interconnect (2). If there is a parasitic contact structure (5) formed between the contact elements (4), which has arisen during the lithographic exposure for producing the contact elements (4) on account of constructively interfering diffraction maxima, then this shorts the second interconnect (2) to the third interconnect (3).

Abstract: An integrated circuit arrangement that has an integrated test structure is provided. The integrated circuit arrangement includes a transistor array having vertical FET selection transistors electrically coupled to storage capacitors of an assigned memory cell array, the storage capacitors being formed vertically into the depth of a substrate in deep trenches. The test structure may enable a plurality of vertical FET selection transistors by a conductive electrode material embedded in an extended deep trench. With a test structure of this type, it is possible to evaluate characteristic values for leakage currents and capacitances at different semiconductor junctions and also between different sections of the integrated circuit arrangement and also to perform reliability stress tests.

Abstract: An array process diagnosis test structure for an integrated circuit including a transistor array composed of vertical FET memory cell access transistors, which are formed into the depth of a substrate in the form of active webs which run parallel in the lateral direction of the circuit is disclosed. Memory cell storage capacitors in the array test structure are formed in deep trenches on the end faces of those sections of the active webs which form the vertical FET transistors. Word lines are arranged along the webs and along parallel intersecting bit lines of the array, outside of which, and on two mutually opposite edges, are located a first and second word line comb. The wordline combs are offset and connected alternately to different word lines. In addition, a first and a second bit line comb are formed on the two other opposing edges of the transistor array mutually offset and each connected to different bit lines.

Abstract: A test structure allows determining a short circuit between trench capacitors in a memory cell array in which the trench capacitors are arranged in matrix form. The test structure has, in two rows of trench capacitors, a connection of the trench capacitors of each row by tunnel structures and/or bridge structures. A contact area for contact connection is provided at each end section of a trench capacitor row.

Abstract: A test structure for determining a doping region of an outer capacitor electrode of a trench capacitor in a memory cell array. The trench capacitors of the memory cell array are arranged in matrix form. The test structure has two parallel rows of trench capacitors. The outer capacitor electrode of each row of trench capacitors is electrically connected to one another and the basic area of at least one trench capacitor of each row is lengthened on the side facing the other row in such a way that the two trench capacitors overlap in a direction transverse to their extent.

Abstract: A test structure for determining the electrical properties of a memory cell in a matrix-like cell array constructed on the basis of the single-sided buried strap concept has a connection between internal electrodes in the storage capacitors in two adjacent memory cells in the direction of the row of active regions in order to produce a series circuit. A first selection transistor and a first storage capacitor in a first memory cell and a second selection transistor and a second storage capacitor in a second memory cell, the active regions of the first and second selection transistors not being connected between the first and second selection transistors via a contact-making bit line.

Abstract: An integrated circuit arrangement which has vertical FET selection transistors and storage capacitors in each case of a transistor array and of an assigned memory cell array, said storage capacitors being formed vertically into the depth of a substrate in deep trenches a test structure is integrated, which enables a plurality of vertical FET selection transistors with one another by a conductive electrode material embedded in an extended deep trench With a test structure of this type, it is possible to evaluate characteristic values for leakage currents and capacitances at different semiconductor junctions and also between different sections of the integrated circuit arrangement and also to perform reliability stress tests.

Abstract: A test structure for determining the resistance of a conducting junction between an active region of a selection transistor and a storage capacitor in a matrix-type cell array where the active regions of the selection transistors are in rows in a first direction and the storage capacitors are in rows in a second direction running perpendicular to the first direction. The conducting junctions between the active regions of the selection transistors and the storage capacitors are formed at overlapping areas of the mutually perpendicular rows each in a single edge region of the overlapping area in the first direction. The active regions of the selection transistors and/or the storage capacitors are connected by tunnel structures or bridge structures in the second direction in the region adjoining the junction to be measured between the active region of the selection transistor and the storage capacitor. This achieves a low-impedance connection to the junction to be measured.

Abstract: A test structure for a memory cell array determines a doping region of an electrode connection that, in a memory cell, connects an inner capacitor electrode of a trench capacitor to an associated selection transistor. The test structure has an electrical contact with a predetermined contact area disposed between a regular matrix configuration of four trench capacitors.

Abstract: A transistor array has vertical FET transistors each connected to a storage capacitor of a memory cell array. Gate electrode strips, which form word lines, of the transistors are located on both sides of active webs running parallel to one another and are connected to a superimposed metal plane by word line or CS contacts. To insulate these word line contacts from the other elements of the transistor array and of the cell array, the word line contacts are located in deep trenches that are introduced into the webs.

Abstract: An array process diagnosis test structure for an integrated circuit including a transistor array composed of vertical FET memory cell access transistors, which are formed into the depth of a substrate in the form of active webs which run parallel in the lateral direction of the circuit is disclosed. Memory cell storage capacitors in the array test structure are formed in deep trenches on the end faces of those sections of the active webs which form the vertical FET transistors. Word lines are arranged along the webs and along parallel intersecting bit lines of the array, outside of which, and on two mutually opposite edges, are located a first and second word line comb. The wordline combs are offset and connected alternately to different word lines. In addition, a first and a second bit line comb are formed on the two other opposing edges of the transistor array mutually offset and each connected to different bit lines.

Abstract: A transistor array has vertical FET transistors each connected to a storage capacitor of a memory cell array. Gate electrode strips, which form word lines, of the transistors are located on both sides of active webs running parallel to one another and are connected to a superimposed metal plane by word line or CS contacts. To insulate these word line contacts from the other elements of the transistor array and of the cell array, the word line contacts are located in deep trenches that are introduced into the webs.

Abstract: A test structure for determining a doping region of an outer capacitor electrode of a trench capacitor in a memory cell array. The trench capacitors of the memory cell array are arranged in matrix form. The test structure has two parallel rows of trench capacitors. The outer capacitor electrode of each row of trench capacitors is electrically connected to one another and the basic area of at least one trench capacitor of each row is lengthened on the side facing the other row in such a way that the two trench capacitors overlap in a direction transverse to their extent.

Abstract: A test structure allows determining a short circuit between trench capacitors in a memory cell array in which the trench capacitors are arranged in matrix form. The test structure has, in two rows of trench capacitors, a connection of the trench capacitors of each row by tunnel structures and/or bridge structures. A contact area for contact connection is provided at each end section of a trench capacitor row.