Abstract: A process for manufacturing a MOS device is described. The process comprising: providing a body of semiconductor material having a surface; forming a stack on the surface of the body, the stack including a first polysilicon region, an intermediate dielectric region arranged on top of the first polysilicon region, and a second polysilicon region arranged on top of the intermediate dielectric region; depositing a passivation layer on top of and laterally to the stack; and forming at least one electrical connection region in direct electrical contact with the first and second polysilicon regions, wherein the electrical connection region is formed laterally with respect to both the first and second polysilicon regions.

Abstract: A MOS device has: a semiconductor body defining a surface; a stack on top of the semiconductor body; and a passivation layer on top of the semiconductor body and covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and separated by an intermediate dielectric region. An electrical connection region extends through the passivation layer as far as the surface of the semiconductor body laterally with respect to, and in contact with, the first and the second polysilicon regions so as to contact them electrically.