Patents by Inventor Valeri Popescu
Valeri Popescu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140331234Abstract: Execution of a plurality of tasks by a processor system are monitored. Based on this monitoring, tasks requiring adjustment of performance resources are identified by calculating at least one of a progress error or a progress limit error for each task. Thereafter, performance resources of the processor system allocated to each identified task are adjusted. Such adjustment can comprise: adjusting a clock rate of at least one processor in the processor system executing the task, adjusting an amount of cache and/or buffers to be utilized by the task, and/or adjusting an amount of input/output (I/O) bandwidth to be utilized by the task. Related systems, apparatus, methods and articles are also described.Type: ApplicationFiled: July 15, 2014Publication date: November 6, 2014Inventors: Gary Allen Gibson, Valeri Popescu
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Publication number: 20140201456Abstract: Techniques are described for controlling processor cache memory within a processor system. Cache occupancy values for each of a plurality of entities executing the processor system can be calculated. A cache replacement algorithm uses the cache occupancy values when making subsequent cache line replacement decisions. In some variations, entities can have occupancy profiles specifying a maximum cache quota and/or a minimum cache quota which can be adjusted to achieve desired performance criteria. Related methods, systems, and articles are also described.Type: ApplicationFiled: March 18, 2014Publication date: July 17, 2014Applicant: VirtualMetrix, Inc.Inventors: Gary Allen Gibson, Valeri Popescu
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Patent number: 8782653Abstract: Execution of a plurality of tasks by a processor system are monitored. Based on this monitoring, tasks requiring adjustment of performance resources are identified by calculating at least one of a progress error or a progress limit error for each task. Thereafter, performance resources of the processor system allocated to each identified task are adjusted. Such adjustment can comprise: adjusting a clock rate of at least one processor in the processor system executing the task, adjusting an amount of cache and/or buffers to be utilized by the task, and/or adjusting an amount of input/output (I/O) bandwidth to be utilized by the task. Related systems, apparatus, methods and articles are also described.Type: GrantFiled: March 25, 2011Date of Patent: July 15, 2014Assignee: VirtualMetrix, Inc.Inventors: Gary Allen Gibson, Valeri Popescu
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Patent number: 8677071Abstract: Techniques are described for controlling processor cache memory within a processor system. Cache occupancy values for each of a plurality of entities executing the processor system can be calculated. A cache replacement algorithm uses the cache occupancy values when making subsequent cache line replacement decisions. In some variations, entities can have occupancy profiles specifying a maximum cache quota and/or a minimum cache quota which can be adjusted to achieve desired performance criteria. Related methods, systems, and articles are also described.Type: GrantFiled: March 25, 2011Date of Patent: March 18, 2014Assignee: Virtualmetrix, Inc.Inventors: Gary Allen Gibson, Valeri Popescu
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Publication number: 20110238919Abstract: Techniques are described for controlling processor cache memory within a processor system. Cache occupancy values for each of a plurality of entities executing the processor system can be calculated. A cache replacement algorithm uses the cache occupancy values when making subsequent cache line replacement decisions. In some variations, entities can have occupancy profiles specifying a maximum cache quota and/or a minimum cache quota which can be adjusted to achieve desired performance criteria. Related methods, systems, and articles are also described.Type: ApplicationFiled: March 25, 2011Publication date: September 29, 2011Inventors: Gary Allen Gibson, Valeri Popescu
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Publication number: 20110239220Abstract: Execution of a plurality of tasks by a processor system are monitored. Based on this monitoring, tasks requiring adjustment of performance resources are identified by calculating at least one of a progress error or a progress limit error for each task. Thereafter, performance resources of the processor system allocated to each identified task are adjusted. Such adjustment can comprise: adjusting a clock rate of at least one processor in the processor system executing the task, adjusting an amount of cache and/or buffers to be utilized by the task, and/or adjusting an amount of input/output (I/O) bandwidth to be utilized by the task. Related systems, apparatus, methods and articles are also described.Type: ApplicationFiled: March 25, 2011Publication date: September 29, 2011Inventors: Gary Allen Gibson, Valeri Popescu
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Publication number: 20020013805Abstract: A low cost network efficiently supporting both event-driven and constant data rate messages is implemented using inexpensive off-the-shelf micro controllers and firmware. The network firmware uses less than 2K bytes for the network hub and less than 1K bytes for the other network nodes A combination of polling and token passing ensures each node can become “Master” and control the network and thus providing for steady data rate transfers. A specially designated “Hub-node” ensures fairness by preventing idling nodes from unnecessarily taking control of the network access. The Hub controls the token advance signal going to all nodes. The client/server protocol with peer/peer capabilities utilizes both master/slave and token passing media access methods.Type: ApplicationFiled: March 21, 2001Publication date: January 31, 2002Inventor: Valeri Popescu
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Patent number: 5987588Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.Type: GrantFiled: August 28, 1998Date of Patent: November 16, 1999Assignee: Hyundai Electronics America, Inc.Inventors: Valeri Popescu, Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner
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Patent number: 5832293Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.Type: GrantFiled: August 15, 1997Date of Patent: November 3, 1998Assignee: Hyundai Electronics America, Inc.Inventors: Valeri Popescu, Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner
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Patent number: 5797025Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.Type: GrantFiled: November 14, 1996Date of Patent: August 18, 1998Assignee: Hyundai Electronics America, Inc.Inventors: Valeri Popescu, Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner
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Patent number: 5708841Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.Type: GrantFiled: September 17, 1996Date of Patent: January 13, 1998Assignee: Hyundai Electronics AmericaInventors: Valeri Popescu, Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner
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Patent number: 5627983Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.Type: GrantFiled: June 6, 1995Date of Patent: May 6, 1997Assignee: Hyundai Electronics AmericaInventors: Valeri Popescu, Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner
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Patent number: 5625837Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.Type: GrantFiled: June 6, 1995Date of Patent: April 29, 1997Assignee: Hyundai Electronics AmericaInventors: Valeri Popescu, Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner
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Patent number: 5592636Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.Type: GrantFiled: June 6, 1995Date of Patent: January 7, 1997Assignee: Hyundai Electronics AmericaInventors: Valeri Popescu, Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner
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Patent number: 5561776Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.Type: GrantFiled: June 6, 1995Date of Patent: October 1, 1996Assignee: Hyundai Electronics AmericaInventors: Valeri Popescu, Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner
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Patent number: 5487156Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.Type: GrantFiled: December 5, 1990Date of Patent: January 23, 1996Inventors: Valeri Popescu, Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner