Patents by Inventor Valeria Bertacco
Valeria Bertacco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11868283Abstract: The increased use of graph algorithms in diverse fields has highlighted their inefficiencies in current chip-multiprocessor (CMP) architectures, primarily due to their seemingly random-access patterns to off-chip memory. Here, a novel computer memory architecture is proposed that processes operations on vertex data in on-chip memory and off-chip memory. The hybrid computer memory architecture utilizes a vertex's degree as a proxy to determine whether to process related operations in on-memory or off-chip memory. The proposed computer memory architecture manages to provide up to 4.0× improvement in performance and 3.8× in energy benefits, compared to a baseline CMP, and up to a 2.0× performance boost over state-of-the-art specialized solutions.Type: GrantFiled: July 17, 2020Date of Patent: January 9, 2024Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Valeria Bertacco, Abraham Addisie
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Patent number: 11748521Abstract: A system includes an electronic circuit. The electronic circuit includes a first set of electronic circuit elements electrically coupled to receive first secret data that was encrypted externally to the electronic circuit according to a data key and decrypt the first secret data based in part on parameters included in the data key. The electronic circuit further includes a second set of electronic circuit elements coupled to generate second secret data by executing one or more operations on the first secret data and a third set of electronic circuit elements coupled to encrypt the second secret data based in part on the parameters included in the data key, thereby providing encrypted second secret data for output.Type: GrantFiled: December 17, 2021Date of Patent: September 5, 2023Assignee: Agita Labs, Inc.Inventors: Todd M Austin, Valeria Bertacco, Alexander Kisil
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Patent number: 11748490Abstract: A computer system includes an ensemble moving target defense architecture that protects the computer system against attack using one or more composable protection layers that change each churn cycle, thereby requiring an attacker to acquire information needed for an attack (e.g., code and pointers) and successfully deploy the attack, before the layers have changed state. Each layer may deploy a respective attack information asset protection providing multiple respective attack protections each churn cycle, wherein the respective attack information asset protections may differ.Type: GrantFiled: December 30, 2021Date of Patent: September 5, 2023Assignee: REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Todd Austin, Valeria Bertacco, Mark Gallagher, Baris Kasikci
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Publication number: 20220277072Abstract: A method of securing a virtual address space against unauthorized access from an unauthorized agent includes generating a superimposed address space corresponding to the virtual address space, dilating the superimposed address space by inserting dununy memory at a plurality of locations in the superimposed address space, and displacing the superimposed address space by shifting a segment of the superimposed address space by a d-bit key. A computer processor includes a memory and a dedicated functional unit in a stage of a pipeline of the computer processor, the computer processor including an instruction that when executed by the dedicated functional unit causes the computer processor to translate one or more pointers between displaced and dilated address spaces of the memory and virtual address spaces of the memory.Type: ApplicationFiled: August 17, 2020Publication date: September 1, 2022Inventors: Todd Austin, Valeria Bertacco, Mark Gallagher, Baris Kasikci, Lauren Biernacki
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Publication number: 20220198067Abstract: A system includes an electronic circuit. The electronic circuit includes a first set of electronic circuit elements electrically coupled to receive first secret data that was encrypted externally to the electronic circuit according to a data key and decrypt the first secret data based in part on parameters included in the data key. The electronic circuit further includes a second set of electronic circuit elements coupled to generate second secret data by executing one or more operations on the first secret data and a third set of electronic circuit elements coupled to encrypt the second secret data based in part on the parameters included in the data key, thereby providing encrypted second secret data for output.Type: ApplicationFiled: December 17, 2021Publication date: June 23, 2022Inventors: Todd M. Austin, Valeria Bertacco, Alexander Kisil
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Publication number: 20220198068Abstract: A system includes an electronic circuit that performs operations on encrypted data. The electronic circuit includes electronic circuit elements electrically coupled to receive an encrypted first secret data block including a first data identifier and to decrypt the encrypted first secret data block. The electronic circuit further includes electronic circuit elements electrically coupled to combine the data identifier and an operation identifier of an operation to be executed to generate an intermediate value; apply a one-way hash function to the intermediate value to generate a second data identifier; and encrypt the second data identifier for outputting.Type: ApplicationFiled: December 17, 2021Publication date: June 23, 2022Inventors: Todd M Austin, Valeria Bertacco, Alexander Kisil
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Publication number: 20220129563Abstract: A computer system includes an ensemble moving target defense architecture that protects the computer system against attack using one or more composable protection layers that change each churn cycle, thereby requiring an attacker to acquire information needed for an attack (e.g., code and pointers) and successfully deploy the attack, before the layers have changed state. Each layer may deploy a respective attack information asset protection providing multiple respective attack protections each churn cycle, wherein the respective attack information asset protections may differ.Type: ApplicationFiled: December 30, 2021Publication date: April 28, 2022Inventors: Todd Austin, Valeria Bertacco, Mark Gallagher, Baris Kasikci
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Patent number: 11232212Abstract: A computer system includes an ensemble moving target defense architecture that protects the computer system against attack using a plurality of composable protection layers that change each churn cycle, thereby requiring an attacker to acquire information needed for an attack (e.g., code and pointers) and successfully deploy the attack, before the layers have changed state. Each layer may deploy a different attack information asset protection providing multiple different attack protections each churn cycle.Type: GrantFiled: August 21, 2019Date of Patent: January 25, 2022Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Todd Austin, Valeria Bertacco, Mark Gallagher, Baris Kasikci
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Publication number: 20220019545Abstract: The increased use of graph algorithms in diverse fields has highlighted their inefficiencies in current chip-multiprocessor (CMP) architectures, primarily due to their seemingly random-access patterns to off-chip memory. Here, a novel computer memory architecture is proposed that processes operations on vertex data in on-chip memory and off-chip memory. The hybrid computer memory architecture utilizes a vertex's degree as a proxy to determine whether to process related operations in on-memory or off-chip memory. The proposed computer memory architecture manages to provide up to 4.0× improvement in performance and 3.8× in energy benefits, compared to a baseline CMP, and up to a 2.0× performance boost over state-of-the-art specialized solutions.Type: ApplicationFiled: July 17, 2020Publication date: January 20, 2022Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Valeria BERTACCO, Abraham ADDISIE
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Publication number: 20200110884Abstract: A computer system includes an ensemble moving target defense architecture that protects the computer system against attack using a plurality of composable protection layers that change each churn cycle, thereby requiring an attacker to acquire information needed for an attack (e.g., code and pointers) and successfully deploy the attack, before the layers have changed state. Each layer may deploy a different attack information asset protection providing multiple different attack protections each churn cycle.Type: ApplicationFiled: August 21, 2019Publication date: April 9, 2020Inventors: Todd Austin, Valeria Bertacco, Mark Gallagher
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Patent number: 9645882Abstract: A state matcher for a logic circuit may detect at least one of a buggy state of the logic circuit, a precursor to a buggy state of the logic circuit and a verified state of the logic circuit based on a plurality of signal values indicative of a state of the logic circuit. A recovery controller for a microprocessor may reconfigure the microprocessor to a trusted feature mode in response to receiving a signal indicating that the microprocessor is in a predefined state and operate the microprocessor in the trusted feature mode for a predetermined period of time.Type: GrantFiled: July 23, 2008Date of Patent: May 9, 2017Assignee: The Regents of the University of MichiganInventors: Valeria Bertacco, Todd Michael Austin, Ilya Wagner
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Patent number: 9411007Abstract: The system and method described herein relate to a bug positioning system for post-silicon validation of a prototype integrated circuit using statistical analysis. Specifically, the bug positioning system samples output and intermediate signals from a prototype chip to generate signatures. Signatures are grouped into passing and failing groups, modeled, and compared to identify patterns of acceptable behavior and unacceptable behavior and locate bugs in space and time.Type: GrantFiled: October 29, 2012Date of Patent: August 9, 2016Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Valeria Bertacco, Andrew DeOrio, Daya Shanker Khudia
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Patent number: 8738349Abstract: Techniques for simulating operation of a connectivity level description of an integrated circuit design are provided, for example, to simulate logic elements expressed through a netlist description. The techniques utilize a host processor selectively partitioning and optimizing the descriptions of the integrated circuit design for efficient simulation on a parallel processor, more particularly a SIMD processor. The description may be segmented into cluster groups, for example macro-gates, formed of logic elements, where the cluster groups are sized for parallel simulation on the parallel processor. Simulation may occur in an oblivious as well as event-driven manner, depending on the implementation.Type: GrantFiled: April 21, 2010Date of Patent: May 27, 2014Assignee: The Regents of the University of MichiganInventors: Valeria Bertacco, Debapriya Chatterjee, Andrew Deorio
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Patent number: 8365110Abstract: A computer executable tool facilitates integrated circuit design and debugging by working directly at the Register Transfer Level, where most design activities take place. The tool determines when an integrated circuit design produces incorrect output responses for a given set of input vectors. The tool accesses the expected responses and returns the signal paths in the integrated circuit that are responsible for the errors along with suggested changes for fixing the errors. The tool may operate at the RTL, which is above the gate-level abstraction which means that the design errors will be much more readily understood to the designer, and may improve scalability and efficiency.Type: GrantFiled: May 27, 2008Date of Patent: January 29, 2013Assignee: The Regents of the University of MichiganInventors: Kai-Hui Chang, Ilya Wagner, Igor Markov, Valeria Bertacco
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Patent number: 8341473Abstract: A microprocessor has a silicon area comprising a plurality of transistors implemented on the silicon area and a fault detection circuit occupying less than 20% of the silicon area and configured to detect faults at runtime in at least 80% of the plurality of transistors.Type: GrantFiled: September 23, 2011Date of Patent: December 25, 2012Assignee: The Regents of the University of MichiganInventors: Valeria Bertacco, Todd Michael Austin, Smitha Shyam, Kypros Constantinides, Sujay Phadke
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Publication number: 20120011422Abstract: A method for detecting microprocessor hardware faults includes sending at least one input signal to a logic block within the microprocessor, collecting an output response to the input signal from the logic block, and determining whether the output response matches an expected output response of the logic block.Type: ApplicationFiled: September 23, 2011Publication date: January 12, 2012Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Valeria Bertacco, Todd Michael Austin, Smitha Shyam, Kypros Constantinides, Sujay Phadke
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Patent number: 8051368Abstract: A method for detecting microprocessor hardware faults includes sending at least one input signal to a logic block within the microprocessor, collecting an output response to the input signal from the logic block, and determining whether the output response matches an expected output response of the logic block.Type: GrantFiled: February 28, 2011Date of Patent: November 1, 2011Assignee: The Regents of the Univeristy of MichiganInventors: Valeria Bertacco, Todd Michael Austin, Smitha Shyam, Kypros Constantinides, Sujay Phadke
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Publication number: 20110257955Abstract: Techniques for simulating operation of a connectivity level description of an integrated circuit design are provided, for example, to simulate logic elements expressed through a netlist description. The techniques utilize a host processor selectively partitioning and optimizing the descriptions of the integrated circuit design for efficient simulation on a parallel processor, more particularly a SIMD processor. The description may be segmented into cluster groups, for example macro-gates, formed of logic elements, where the cluster groups are sized for parallel simulation on the parallel processor. Simulation may occur in an oblivious as well as event-driven manner, depending on the implementation.Type: ApplicationFiled: April 21, 2010Publication date: October 20, 2011Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Valeria Bertacco, Debapriya Chatterjee, Andrew Deorio
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Publication number: 20110214014Abstract: A method for detecting microprocessor hardware faults includes sending at least one input signal to a logic block within the microprocessor, collecting an output response to the input signal from the logic block, and determining whether the output response matches an expected output response of the logic block.Type: ApplicationFiled: February 28, 2011Publication date: September 1, 2011Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Valeria Bertacco, Todd Michael Austin, Smitha Shyam, Kypros Constantinides, Sujay Phadke
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Patent number: 7966538Abstract: A method for detecting microprocessor hardware faults includes sending at least one input signal to a logic block within the microprocessor, collecting an output response to the input signal from the logic block, and determining whether the output response matches an expected output response of the logic block.Type: GrantFiled: October 16, 2008Date of Patent: June 21, 2011Assignee: The Regents of the University of MichiganInventors: Valeria Bertacco, Todd Michael Austin, Smitha Shyam, Kypros Constantinides, Sujay Phadke